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DATA SHEET
PD6P8, 6P8A, 6P8B
4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROL TRANSMISSION
MOS INTEGRATED CIRCUIT
DESCRIPTION
The PD6P8, 6P8A, 6P8B are microcontrollers for infrared remote control transmitters and are provided with a one-time PROM as the program memory. Because users can write programs for the PD6P8, 6P8A, 6P8B, They are ideal for program evaluation and smallscale production of application systems that use the PD67A, 67B, 68A, 68B. When reading this document, also refer to the following documents.
PD67, 67A, 68, 68A, 69 Data Sheet: U14935E PD67B, 68B Data Sheet: U16792E
FEATURES
* Program memory (one-time PROM): 2026 x 10 bits * Data memory (RAM): 32 x 4 bits * On-chip carrier generator for infrared remote control: The high-level and low-level width can be set separately from 250 ns to 64 s (@ fX = 4 MHz operation) via modulo registers * 9-bit programmable timer: 1 channel * Instruction execution time: 16 s (@ fX = 4 MHz) * Stack level: 1 level (stack RAM is for data memory RF as well) * I/O pins (KI/O): 8 units 4 units * Input pins (KI): 2 units * Sense input pins (S0, S2): * S1/LED pin (I/O): 1 unit (when in output mode, this is the remote control transmission display pin) * Power supply voltage: VDD = 1.9 to 3.6 V * Operating ambient temperature: TA = -40 to +85C * Oscillator frequency: fX = 3.5 to 4.5 MHz * On-chip POC circuit and RAM retention detector * On-chip oscillator (PD6P8B)
APPLICATIONS
Infrared remote control transmitters (for AV and household electric appliances)
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. U17848EJ3V0DS00 (3rd edition) Date Published December 2007 N Printed in Japan
The mark shows major revised points.
2006
PD6P8, 6P8A, 6P8B
ORDERING INFORMATION
Part Number Package 20-pin plastic SSOP (7.62 mm (300)) 20-pin plastic SSOP (7.62 mm (300))
PD6P8MC-5A4-A

PD6P8AMC-5A4-A
PD6P8BMC-5A4-ANote 20-pin plastic SSOP (7.62 mm (300))
Note Under development Remark Products that have the part numbers suffixed by "-A" are lead-free products.
PD6P8 PIN CONFIGURATION (TOP VIEW)
20-pin plastic SSOP (7.62 mm (300)) (1) Normal operation mode
KI/O6 KI/O7 S0 S1/LED REM VDD XOUT XIN GND S2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0
(2) PROM programming mode
D6 D7 CLK (L) VDD XOUT XIN GND VPP 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 D5 D4 D3 D2 D1 D0 MD3 MD2 MD1 MD0
Caution The item in parentheses indicates the processing of pins not used in the PROM programming mode. L: Connect each of these pins to GND via a pull-down resistor.
2
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
PD6P8A PIN CONFIGURATION (TOP VIEW)
20-pin plastic SSOP (7.62 mm (300)) (1) Normal operation mode
KI/O6 KI/O7 S0 S1/LED REM VDD XOUT XIN GND S2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0
(2) PROM programming mode
(F) SO SCLK SI (F) VDD XOUT XIN GND VPP 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 (F) (F) (F) (F) (F) (F) (F) (F) (F) (F)
Caution The item in parentheses indicates the processing of pins not used in the PROM programming mode. F: These pins are pulled down internally, so leave them open.
Data Sheet U17848EJ3V0DS
3
PD6P8, 6P8A, 6P8B
PD6P8B PIN CONFIGURATION (TOP VIEW) 20-pin plastic SSOP (7.62 mm (300)) (1) Normal operation mode
KI/O6 KI/O7 S0 S1/LED REM VDD IC S3 GND S2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0
(2) PROM programming mode
(F) SO SCLK SI (F) VDD (F) (F) GND VPP 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 (F) (F) (F) (F) (F) (F) (F) (F) (F) (F)
Caution The item in parentheses indicates the processing of pins not used in the PROM programming mode. F: These pins are pulled down internally, so leave them open.
4
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
BLOCK DIAGRAM
REM
Carrier generator
4 CPU core Onetime PROM
Port KI
4
KI0 to KI3
8
Port KI/O
8
KI/O0 to KI/O7
S1/LED
9-bit timer
3
Port S
3
S0, S1/LED, S2
RAM
System control
XIN XOUT VDD GND
LIST OF FUNCTIONS
Item ROM capacity RAM capacity Stack I/O pins
PD6P8
2026 x 10 bits One-time PROM 32 x 4 bits 1 level (shared with RF of RAM) Key input (KI):
PD6P8A
PD6P8B
Key I/O (KI/O): Key expansion input (S0, S1, S2): Remote control transmission display output (LED): Number of keys Clock frequency Instruction execution time Carrier frequency Timer POC circuit RAM retention detector Internal oscillator Programming method Supply voltage Operating ambient temperature Package 32 keys 56 keys (when expanded by key expansion input) Ceramic oscillation fX = 3.5 to 4.5 MHz 16 s (@ fX = 4 MHz)
4 8 3 1
pins pins pins pin (shared with S1 pin)
The high-level and low-level width can be set separately from 250 ns to 64 s (@ fX = 4 MHz operation) via modulo registers 9-bit programmable timer: 1 channel, timer clock: fX/64 On chip On chip Not available Parallel VDD = 1.9 to 3.6 V TA = -40 to +85C 20-pin plastic SSOP (7.62 mm (300)) Serial On chip
Data Sheet U17848EJ3V0DS
5
PD6P8, 6P8A, 6P8B
CONTENTS
1. PIN FUNCTIONS .........................................................................................................................
1.1 1.2 1.3 1.4 1.5 Normal Operation Mode ....................................................................................................................
8
8
PROM Programming Mode ............................................................................................................... 10 Pins I/O Circuits ................................................................................................................................. 11 Recommended Connection of Unused Pins ................................................................................... 12 Notes on Using KI Pin After Reset ................................................................................................... 12
2. DIFFERENCES BETWEEN PD67A, 67B, 68A, 68B, AND PD6P8, 6P8A, 6P8B .................. 13 3. INTERNAL CPU FUNCTIONS .................................................................................................. 14
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Program Counter (PC): 11 Bits ........................................................................................................ 14 Stack Pointer (SP): 1 Bit ................................................................................................................... 14 Address Stack Register (ASR (RF)): 11 Bits ................................................................................... 14 Program Memory (One-Time PROM): 2,026 Steps x 10 Bits ......................................................... 15 Data Memory (RAM): 32 x 4 Bits ...................................................................................................... 16 Data Pointer (DP): 12 Bits ................................................................................................................. 17 Accumulator (A): 4 Bits .................................................................................................................... 17 Arithmetic and Logic Unit (ALU): 4 Bits .......................................................................................... 17 Flags ................................................................................................................................................... 18 3.9.1 3.9.2 Status flag (F) .......................................................................................................................... 18 Carry flag (CY) ........................................................................................................................ 18
4. PORT REGISTERS (PX) ........................................................................................................... 19
4.1 4.2 KI/O Port (P0) ....................................................................................................................................... 20 KI Port/Special Ports (P1) ................................................................................................................. 20 4.2.1 4.2.2 4.2.3 4.2.4 4.3 4.4 4.3.1 KI port (P11: bits 4 to 7 of P1) .................................................................................................. 20 S0 port (bit 2 of P1) .................................................................................................................. 21 S1/LED port (bit 3 of P1) .......................................................................................................... 21 S2 port (bit 1 of P1) .................................................................................................................. 21 RAM retention flag (bit 3 of P3) ............................................................................................... 23
Control Register 0 (P3) ..................................................................................................................... 22 Control Register 1 (P4) ..................................................................................................................... 25
5. TIMER ......................................................................................................................................... 26
5.1 5.2 5.3 Timer Configuration .......................................................................................................................... 26 Timer Operation ................................................................................................................................. 27 Carrier Output .................................................................................................................................... 29 5.3.1 5.3.2 5.4 Carrier output generator .......................................................................................................... 29 Carrier output control .............................................................................................................. 30
Software Control of Timer Output ................................................................................................... 32
6. STANDBY FUNCTION ............................................................................................................... 33
6.1 6.2 6.3 Outline of Standby Function ............................................................................................................ 33 Standby Mode Setting and Release ................................................................................................. 34 Standby Mode Release Timing ........................................................................................................ 36
7. RESET ......................................................................................................................................... 37 6
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
8. POC CIRCUIT ............................................................................................................................ 38
8.1 8.2 Functions of POC Circuit .................................................................................................................. 39 Oscillation Check at Low Supply Voltage ....................................................................................... 39
9. SYSTEM CLOCK OSCILLATOR (PD6P8, 6P8A) .................................................................. 40 10. INSTRUCTION SET ................................................................................................................... 41
10.1 Machine Language Output by Assembler ....................................................................................... 10.2 Circuit Symbol Description .............................................................................................................. 10.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table ............................... 10.4 Accumulator Manipulation Instructions .......................................................................................... 10.5 I/O Instructions .................................................................................................................................. 10.6 Data Transfer Instructions ................................................................................................................ 10.7 Branch Instructions .......................................................................................................................... 10.8 Subroutine Instructions .................................................................................................................... 10.9 Timer Operation Instructions ........................................................................................................... 10.10 Others ................................................................................................................................................. 41 42 43 47 50 51 53 54 55 58
11. ASSEMBLER RESERVED WORDS ........................................................................................ 60
11.1 Mask Option Directives ..................................................................................................................... 60 11.1.1 OPTION and ENDOP quasi-directives .................................................................................... 60 11.1.2 Mask option definition quasi-directives ................................................................................... 60
12. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY) (PD6P8) ................. 61
12.1 Operating Mode When Writing/Verifying Program Memory .......................................................... 61 12.2 Program Memory Writing Procedure ............................................................................................... 62 12.3 Program Memory Reading Procedure ............................................................................................. 63
13. WRITING AND VERIFICATION OF ONE-TIME PROM (PROGRAM MEMORY) (PD6P8A, 6P8B) ......... 64
13.1 13.2 13.3 13.4 Initialization ........................................................................................................................................ Serial Communication Format ......................................................................................................... Writing of Program Memory ............................................................................................................. Reading of Program Memory ........................................................................................................... 64 65 66 66
14. ELECTRICAL SPECIFICATIONS (PD6P8) ............................................................................. 67 15. ELECTRICAL SPECIFICATIONS (PD6P8A) .......................................................................... 74 16. ELECTRICAL SPECIFICATIONS (PD6P8B) (TARGET) ........................................................ 79 17. CHARACTERISTIC CURVES (REFERENCE VALUES) (PD6P8) ....................................... 84 18. APPLICATION CIRCUIT EXAMPLE .......................................................................................... 85 19. PACKAGE DRAWING ................................................................................................................ 88 20. RECOMMENDED SOLDERING CONDITIONS .......................................................................... 89 APPENDIX A. DEVELOPMENT TOOLS ......................................................................................... 90 APPENDIX B. EXAMPLE OF REMOTE CONTROL TRANSMISSION FORMAT (In the case of NEC transmission format in command one-shot transmission mode) ........ 91
Data Sheet U17848EJ3V0DS
7
PD6P8, 6P8A, 6P8B
1. PIN FUNCTIONS 1.1 Normal Operation Mode
(1) PD6P8, 6P8A
Pin No. 1 2 15 to 20 3 Symbol KI/O0 to KI/O7 Function 8-bit I/O port. I/O mode can be switched in 8-bit units. In input mode, a pull-down resistor is added. In output mode, these pins can be used as a key scan outputs from the key matrix. Input port. This pin can also be used as a key return input from the key matrix. In input mode, the use of a pull-down resistor for the S0 and S1 ports can be specified by software in 2-bit units. If input mode is released by software, this pin is placed in the OFF mode and enters a high-impedance state. I/O port. In input mode (S1), this pin can also be used as a key return input from the key matrix. The use of a pull-down resistor for the S0 and S1 ports can be specified by software in 2-bit units. In output mode (LED), this pin becomes the remote control transmission display output (active low). When the remote control carrier is output from the REM output, this pin outputs a low level from the LED output in synchronization with the REM signal. Infrared remote control transmission output. The output is active high. The carrier high-level and low-level width can each be freely set in a range of 250 ns to 64 s (@ fX = 4 MHz) using software. Power supply These pins are connected to system clock ceramic resonators. GND pin Input port. The use of the STOP mode release of the S2 port can be specified by software. When using this pin as a key input from the key matrix, enable the use of the STOP mode release (at this time, a pull-down resistor is connected internally.) When the STOP mode release is disabled, this pin can be used as an input port that does not release the STOP mode even if the release condition is established (at this time, a pull-down resistor is not connected internally.) 4-bit input port. These pins can be used as key return inputs to the key matrix. The use of pull-down resistors can be specified by software in 4-bit units. Output Format CMOS Push-pullNote 1 After Reset High-level output
S0
--
High-impedance (OFF mode)
4
S1/LED
CMOS push-pull
High-level output (LED)
5
REM
CMOS push-pull
Low-level output
6 7 8 9 10
VDD XOUT XIN GND S2
-- --
-- Low level (oscillation stopped) -- Input (high impedance, STOP mode release cannot be used)
-- --
11 to 14
KI0 to KI3Note 2
--
Input (low-level)
Notes 1. Note that the drive capability of the low-level output side is held low. 2. In order to prevent malfunction, do not input a high-level signal to pins KI0 to KI3 (leaving these pins open is possible, however, when these pins are left open, do not disconnect any connected pull-down resistors) when POC is released due to supply voltage startup.
8
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
(2) PD6P8B
Pin No. 1 2 15 to 20 3 Symbol KI/O0 to KI/O7 Function 8-bit I/O port. I/O mode can be switched in 8-bit units. In input mode, a pull-down resistor is added. In output mode, these pins can be used as a key scan outputs from the key matrix. Input port. This pin can also be used as a key return input from the key matrix. In input mode, the use of a pull-down resistor for the S0 and S1 ports can be specified by software in 2-bit units. If input mode is released by software, this pin is placed in the OFF mode and enters a high-impedance state. I/O port. In input mode (S1), this pin can also be used as a key return input from the key matrix. The use of a pull-down resistor for the S0 and S1 ports can be specified by software in 2-bit units. In output mode (LED), this pin becomes the remote control transmission display output (active low). When the remote control carrier is output from the REM output, this pin outputs a low level from the LED output in synchronization with the REM signal. Infrared remote control transmission output. The output is active high. The carrier high-level and low-level width can each be freely set in a range of 250 ns to 64 s (@ fX = 4 MHz) using software. Power supply Internally connected pin GND pin Input port. The use of the STOP mode release of the S2 and S3 ports can be specified by software. When using these pins as a key input from the key matrix, enable the use of the STOP mode release (at this time, a pull-down resistor is connected internally.) When the STOP mode release is disabled, these pins can be used as an input port that does not release the STOP mode even if the release condition is established (at this time, a pull-down resistor is not connected internally.) 4-bit input port. These pins can be used as key return inputs to the key matrix. The use of pull-down resistors can be specified by software in 4-bit units. Output Format CMOS Push-pullNote 1 After Reset High-level output
S0
--
High-impedance (OFF mode)
4
S1/LED
CMOS push-pull
High-level output (LED)
5
REM
CMOS push-pull
Low-level output
6 7 9 8 10
VDD IC GND S3 S2
-- -- -- --
-- -- -- Input (high impedance, STOP mode release cannot be used)
11 to 14
KI0 to KI3Note 2
--
Input (low-level)
Notes 1. Note that the drive capability of the low-level output side is held low. 2. In order to prevent malfunction, do not input a high-level signal to pins KI0 to KI3 (leaving these pins open is possible, however, when these pins are left open, do not disconnect any connected pull-down resistors) when POC is released due to supply voltage startup.
Data Sheet U17848EJ3V0DS
9
PD6P8, 6P8A, 6P8B
1.2 PROM Programming Mode
(1) PD6P8
Pin No. 1, 2 15 to 20 3 CLK Clock input for updating address when writing/verifying program memory 6 VDD Power Supply Supply +3 V to this pin when writing/verifying program memory. 7 8 9 10 XOUT XIN GND VPP Clock necessary for writing program memory. Connect a 4 MHz ceramic resonator to these pins. GND Supplies voltage for writing/verifying program memory. Apply +10.5 V to this pin. 11 to 14 MD0 to MD3 Input for selecting operation mode when writing/verifying program memory Input - Input - - - Input Symbol D0 to D7 Function 8-bit data I/O when writing/verifying program memory I/O I/O
(2) PD6P8A
Pin No. 2 3 4 6 Symbol SO SCLK SI VDD Function Serial data output when verifying program memory Clock input when writing/verifying program memory Serial data input when writing program memory Power Supply Supply +3 V to this pin when writing/verifying program memory. 7 8 9 10 XOUT XIN GND VPP Clock necessary for writing program memory. Connect a 4 MHz ceramic resonator to these pins. GND Supplies voltage for writing/verifying program memory. Apply +10.5 V to this pin. - Input - - Output Input Input - I/O

(3) PD6P8B
Pin No. 2 3 4 6 Symbol SO SCLK SI VDD Function Serial data output when verifying program memory Clock input when writing/verifying program memory Serial data input when writing program memory Power Supply Supply +3 V to this pin when writing/verifying program memory. 9 10 GND VPP GND Supplies voltage for writing/verifying program memory. Apply +10.5 V to this pin. - - Output Input Input - I/O
10
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
1.3 Pins I/O Circuits
The I/O circuits of the PD6P8, 6P8A, 6P8B pins are shown in partially simplified forms below. (1) KI/O0 to KI/O7 (4) S0
VDD Data Output latch
Input buffer
P-ch
OFF mode
Output disable N-chNote 1
Selector
Standby release Pull-down flag
Input buffer
N-ch
N-ch
(5) S1/LED (2) KI0 to KI3
REM output latch
Standby release Input buffer
VDD
P-ch
Output disable Standby release
Pull-down flag N-ch
N-ch
Input buffer
Pull-down flag
N-ch
(3) REM
VDD
(6) S2, S3Note 2
Standby release Input buffer
P-ch Data Output latch N-ch
Carrier generator
STOP release ON/OFF
N-ch
Notes 1. The drive capability is held low. 2. PD6P8B only
Data Sheet U17848EJ3V0DS
11
PD6P8, 6P8A, 6P8B
1.4 Recommended Connection of Unused Pins
The following connections are recommended for unused pins in the normal operation mode. Table 1-1. Connections for Unused Pins
Connection Inside the Microcontroller KI/O0-KI/O7 Input mode Output mode REM ICNote S1/LED S0 S2, S3Note KI0-KI3 -- High-level output -- -- Output mode (LED) setting OFF mode setting -- -- Directly connect these pins to GND Outside the Microcontroller Leave open
Pin
Note
PD6P8B only
Caution The I/O mode and the pin output level are recommended to be fixed by setting them repeatedly in each loop of the program.
1.5 Notes on Using KI Pin After Reset
In order to prevent malfunction, do not input a high-level signal to pins KI0 to KI3 (leaving these pins open is possible, however, when these pins are left open, do not disconnect any connected pull-down resistors) when POC is released due to supply voltage startup.
12
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
2. DIFFERENCES BETWEEN PD67A, 67B, 68A, 68B, AND PD6P8, 6P8A, 6P8B
Table 2-1 shows the differences between the PD67A, 67B, 68A, 68B, and PD6P8, 6P8A, 6P8B. The only differences between these models are the program memory, RAM retention detection voltage, internal oscillator, POC detection voltage, and supply voltage; the other CPU functions and internal peripheral hardware are the same. The electrical specifications also differ slightly. For the electrical specifications, refer to the data sheet of each model. Table 2-1. Differences Between PD67A, 67B, 68A, 68B, and PD6P8, 6P8A, 6P8B
Item ROM
PD6P8
2026 x 10 bits
PD6P8A
PD6P8B
PD67A
Mask ROM 1002 x 10 bits VPOC = 1.85 V (TYP.) VID = 1.4 V (TYP.)
PD67B
PD68A
2026 x 10 bits
PD68B
One-time PROM
POC detection voltage
VPOC = 1.8 V (TYP.)
VPOC = 1.5 V (TYP.) VID = 1.5 V (TYP.) -
VPOC = 1.85 V (TYP.) VID = 1.4 V (TYP.)
VPOC = 1.5 V (TYP.) VID = 1.5 V (TYP.)
RAM retention detection voltage Internal oscillator
VID = 1.8 V (TYP.) -
VID = 1.6 V (TYP.) fX = 4 MHz (TYP.)
Supply voltage
VDD = 1.9 to 3.6 V
VDD = 2.0 to 3.6 V
VDD = 1.65 to 3.6 V
VDD = 2.0 to 3.6 V
VDD = 1.65 to 3.6 V
Electrical specifications Some electrical specifications, such as data retention voltage and current consumption, differ. Refer to data sheet of each model for details.
Data Sheet U17848EJ3V0DS
13
PD6P8, 6P8A, 6P8B
3. INTERNAL CPU FUNCTIONS 3.1 Program Counter (PC): 11 Bits
The program counter (PC) is a binary counter that holds the address information of the program memory. Figure 3-1. Program Counter Configuration
PC PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
The PC contains the address of the instruction that should be executed next. Normally, the counter contents are automatically incremented in accordance with the instruction length (byte count) each time an instruction is executed. However, when executing jump instructions (JMP, JC, JNC, JF, JNF), the PC contains the jump destination address written in the operand. When executing the subroutine call instruction (CALL), the call destination address written in the operand is entered in the PC after the PC contents at the time are saved in the address stack register (ASR). If the return instruction (RET) is executed after the CALL instruction is executed, the address saved in the ASR is restored to the PC. After reset, the value of the PC becomes "000H".
3.2 Stack Pointer (SP): 1 Bit
This is a 1-bit register that holds the status of the address stack register. The stack pointer contents are incremented when the call instruction (CALL) is executed and decremented when the return instruction (RET) is executed. When reset, the stack pointer contents are cleared to 0. When the stack pointer overflows (stack level 2 or more) or underflows, the CPU is defined as hung up, a system reset signal is generated, and the PC becomes 000H. As no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer by means of a program.
3.3 Address Stack Register (ASR (RF)): 11 Bits
The address stack register saves the return address of the program after a subroutine call instruction is executed. The lower 8 bits are allocated in RF of the data memory as a alternate-function RAM. The register holds the ASR value even after the RET instruction is executed. After reset, it holds the previous data (undefined when turning on the power). Caution If RF is accessed as the data memory, the higher 4 bits become undefined. Figure 3-2. Address Stack Register Configuration
RF ASR ASR10 ASR9 ASR8 ASR7 ASR6 ASR5 ASR4 ASR3 ASR2 ASR1 ASR0
14
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
3.4 Program Memory (One-Time PROM): 2,026 Steps x 10 Bits
The one-time PROM consists of 10 bits per step, and is addressed by the program counter. The program memory stores programs and table data, etc. The 22 steps from FEAH to FFFH cannot be used in the test program area. Figure 3-3. Program Memory Map
10 bits 0 0 0H
Page 0
3 F FH 4 0 0H
Page 1 7E9H 7 EAH 7 F FH
Test program areaNote
Note The test program area is designed so that a program or data placed in either of them by mistake is returned to the 000H address.
Data Sheet U17848EJ3V0DS
15
PD6P8, 6P8A, 6P8B
3.5 Data Memory (RAM): 32 x 4 Bits
The data memory, which is a static RAM consisting of 32 x 4 bits, is used to retain processed data. The data memory is sometimes processed in 8-bit units. R0 can be used as the ROM data pointer. RF is also used as the ASR. After reset, R0 is cleared to 00H and R1 to RF retain the previous data (undefined when turning on the power). Figure 3-4. Data Memory Configuration
R1n (higher 4 bits) R0n (lower 4 bits) Note 1 R0 R10 R00 R1 R11 R01 R2 R12 R02 R3 R13 R03 R4 R14 R04 R5 R15 R05 R6 R16 R06 R7 R17 R07 R8 R18 R08 R9 R19 R09 RA R1A R0A RB R1B R0B RC R1C R0C RD R1D R0D RE R1E R0E Note 2 RF R1F R0F
Notes 1. R0 alternately functions as the ROM data pointer (refer to 3.6 Data Pointer (DP)). 2. RF alternately functions as the PC address stack (refer to 3.3 Address Stack Register (ASR (RF)).
16
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
3.6 Data Pointer (DP): 12 Bits
The ROM data table can be referenced by setting the ROM address in the data pointer to call the ROM contents. The lower 8 bits of the ROM address are specified by R0 of the data memory; and the higher 4 bits by bits 4 to 7 of the P3 register (CR0). After reset, the pointer contents become 000H. Figure 3-5. Data Pointer Configuration
P3 register b7 P3 0 b6 DP10 b5 DP9 b4 DP8 DP7 DP6 R10 DP5 DP4 DP3 DP2 R00 DP1 DP0 R0
3.7 Accumulator (A): 4 Bits
The accumulator, which refers to a register consisting of 4 bits, plays a leading role in performing various operations. After reset, the accumulator contents are left undefined. Figure 3-6. Accumulator Configuration
A3
A2
A1
A0
A
3.8 Arithmetic and Logic Unit (ALU): 4 Bits
The arithmetic and logic unit (ALU), which refers to an arithmetic circuit consisting of 4 bits, executes simple (mainly logical) operations.
Data Sheet U17848EJ3V0DS
17
PD6P8, 6P8A, 6P8B
3.9 Flags
3.9.1 Status flag (F) Pin and timer statuses can be checked by executing the STTS instruction to check the status flag. The status flag is set (to 1) in the following cases. * If the condition specified with the operand is met when the STTS instruction is executed * When standby mode is released. * When the release condition is met at the point of executing the HALT instruction. (In this case, the system does not enter the standby mode.) Conversely, the status flag is cleared (to 0) in the following cases: * If the condition specified with the operand is not met when the STTS instruction is executed. * When the status flag has been set (to 1), the HALT instruction executed, but the release condition is not met at the point of executing the HALT instruction. (In this case, the system does not enter the standby mode.) Table 3-1. Conditions for Status Flag (F) to Be Set by STTS Instruction
Operand Value of STTS Instruction b3 0 b2 0 0 1 1 1 b1 0 1 1 0 b0 0 1 0 1 High level is input to at least one of KI pins. High level is input to at least one of KI pins. High level is input to at least one of KI pins. The down counter of the timer is 0. [The following condition is added in addition to the above.] High level is input to at least one of S0Note 1, S1Note 1, or S2Note 2 pins.
Condition for Status Flag (F) to Be Set
Either of the combinations of b2, b1, and b0 above.
Notes 1. The S0 and S1 pins must be set to input mode (bit 2 and bit 0 of the P4 register are set to 0 and 1, respectively). 2. The use of STOP mode release for the S2 pin must be enabled (bit 3 of the P4 register is set to 1). 3.9.2 Carry flag (CY) The carry flag is set (to 1) in the following cases: * If the ANL instruction or the XRL instruction is executed when bit 3 of the accumulator is 1 and bit 3 of the operand is 1. * If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is 1. * If the INC instruction or the SCAF instruction is executed when the value of the accumulator is 0FH. The carry flag is cleared (to 0) in the following cases: * If the ANL instruction or the XRL instruction is executed when at least either bit 3 of the accumulator or bit 3 of the operand is 0. * If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is 0. * If the INC instruction or the SCAF instruction is executed when the value of the accumulator is other than 0FH. * If the ORL instruction is executed. * When data is written to the accumulator by the MOV instruction or the IN instruction.
18
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
4. PORT REGISTERS (PX)
The KI/O port, the KI port, the special ports (S0, S1/LED, S2), and the control registers are treated as port registers. After reset, the port register values are as shown below. Figure 4-1. Port Register Configuration
Port register P0 P10 KI/O7 KI/O6 KI/O5 KI/O4 P1 P11 KI3 KI2 KI1 KI0 S1/LED S0 P01 S2 1 0000x000BNote 2 P03 DP9 DP8 RAM retention flag - - - 26H P04 S0 mode KI/O3 KI/O2 P00 KI/O1 KI/O0 xxxx11x1BNote 1 FFH After reset
P3 (control register 0) P13 DP11 DP10
P4 (control register 1) P14 0 0
S0/S1 KI S2 S1/LED mode KI/O mode Pull-down Pull-down STOP release
Notes 1. x: Refers to the value based on the KI and S2 pin state. 2. x: Refers to the value based on decrease of power supply voltage (0 when VDD VID) Remark VID: RAM retention detection voltage Table 4-1. Relationship Between Ports and Reading/Writing
Input Mode Read KI/O KI S0 S1/LED S2 Pin state Pin state Pin state Pin state Pin state Write Output latch -- -- -- -- Note Pin state -- Output Mode Read Output latch -- Write Output latch -- -- -- --
Port Name
Note When in OFF mode, "1" is always read.
Data Sheet U17848EJ3V0DS
19
PD6P8, 6P8A, 6P8B
4.1 KI/O Port (P0)
The KI/O port is an 8-bit I/O port for key scan output. I/O mode is set by bit 1 of the P4 register. If a read instruction is executed, the pin state can be read in input mode, whereas the output latch contents can be read in output mode. If a write instruction is executed, data can be written to the output latch regardless of input or output mode. After reset, the port is placed in output mode and the value of the output latch (P0) becomes 1111 1111B. The KI/O port incorporates a pull-down resistor, allowing pull-down in input mode only. Caution When a key is double-pressed, a high-level output and a low-level output may conflict at the KI/O port. To avoid this, the low-level output current of the KI/O port is held low. Therefore, be careful when using the KI/O port for purposes other than key scan output. The KI/O port is designed so that even when connected directly to VDD within the normal supply voltage range (VDD = 1.9 to 3.6 V), no problem occurs. Table 4-2. KI/O Port (P0)
Bit Name b7 KI/O7 b6 KI/O6 b5 KI/O5 b4 KI/O4 b3 KI/O3 b2 KI/O2 b1 KI/O1 b0 KI/O0
b0 to b7: When reading: When writing:
In input mode, the KI/O pin's state is read. In output mode, the KI/O pin's output latch contents are read. Data is written to the KI/O pin's output latch regardless of input or output mode.
4.2 KI Port/Special Ports (P1)
4.2.1 KI port (P11: bits 4 to 7 of P1) The KI port is a 4-bit input port for key input. The pin state can be read. The use of a pull-down resistor for the KI port can be specified in 4-bit units by software using bit 5 of the P4 register. After reset, a pull-down resistor is connected. Table 4-3. KI/Special Port Register (P1)
Bit Name b7 KI3 b6 KI2 b5 KI1 b4 KI0 b3 S1/LED b2 S0 b1 S2 b0
Fixed to "1"
b1: b2: b3:
The state of the S2 pin is read (read only). In input mode, state of the S0 pin is read (read only). In OFF mode, this bit is fixed to 1. The state of the S1/LED pin is read regardless of input/output mode (read only).
b4 to b7: The state of the KI pin is read (read only). Caution In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when POC is released by supply voltage rising (Can be left open. When open, leave the pulldown resistor connected).
20
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
4.2.2 S0 port (bit 2 of P1) The S0 port is an input/OFF mode port. The pin state can be read by setting this port to input mode using bit 0 of the P4 register. In input mode, the use of a pull-down resistor for the S0 and S1/LED port can be specified in 2-bit units by software using bit 4 of the P4 register. If input mode is released (thus set to OFF mode), the pin becomes high-impedance but is configured so that through current does not flow internally. In OFF mode, 1 can be read regardless of the pin state. After reset, S0 is set to OFF mode, thus becoming high-impedance. 4.2.3 S1/LED port (bit 3 of P1) The S1/LED port is an I/O port. Input or output mode can be set using bit 2 of the P4 resister. The pin state can be read in both input mode and output mode. When in input mode, the use of a pull-down resistor for the S0 and S1/LED ports can be specified in 2-bit units by software using bit 4 of the P4 register. When in output mode, the pull-down resistor is automatically disconnected and this pin becomes the remote control transmission display pin (refer to 5 TIMER). After reset, S1/LED is placed in output mode, and a high level is output. 4.2.4 S2 port (bit 1 of P1) The S2 port is an input port. Use of STOP mode release for the S2 port can be specified by bit 3 of the P4 register. When using the pin as a key input from a key matrix, enable (bit 3 of the P4 register is set to 1) the use of STOP mode release (at this time, a pull-down resistor is connected internally.) When STOP mode release is disabled (bit 3 of the P4 register is set to 0), it can be used as an input port that does not release the STOP mode even if the release condition is met (at this time, a pull-down resistor is not connected internally.) The state of the pin can be read in both cases. After reset, S2 is set to input mode where the STOP mode release is disabled, and enters a high-impedance state.
Data Sheet U17848EJ3V0DS
21
PD6P8, 6P8A, 6P8B
4.3 Control Register 0 (P3)
Control register 0 consists of 8 bits. The contents that can be controlled are as shown below. After reset, the register becomes 0000 x000BNote. Note x: Refers to the value based on a decrease of power supply voltage (0 when VDD VID) Remark VID: RAM retention detection voltage Table 4-4. Control Register 0 (P3)
Bit Name DP11 Setting 0 1 After reset 0 1 0 b7Note b6 b5 b4 b3 RAM retention flag Retainable 0 0 0 0 b2 b1 -- b0
DP (Data Pointer) DP10 0 1 0 DP9 0 1 0 DP8 0 1 0
Not retainable Fixed to 0
b3:
RAM retention flag. For function details, refer to 4.3.1 RAM retention flag (bit 3 of P3).
b4 to b7: Specify the higher bits of the ROM data pointer (DP8 to DP11). Note Set b7 to 0 in the case of the PD6P8, 6P8A, 6P8B.
22
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
4.3.1 RAM retention flag (bit 3 of P3) The RAM retention flag indicates whether the supply voltage has fallen below the level at which the contents of the RAM are lost while the battery is being exchanged or when the battery voltage has dropped. This flag is at bit 3 of control register 0 (P3). It is cleared to 0 if the supply voltage drops below the RAM retention detection voltage. If this flag is 0, it can be judged that the RAM contents have been lost or that power has just been applied. This flag can be used to initialize the RAM via software. After initializing the RAM and writing the necessary data to it, set this RAM retention flag to 1 by software. At this time, 1 means that data has been set to the RAM. Figure 4-2. Supply Voltage Transition and Detection Voltage (PD6P8)
VDD
VPOC/VID
POC detection voltage/ RAM retention detection voltage VPOC = VID = 1.8 V (TYP.) (A)
0V (1) RAM retention flag (2) (3) (4)
t
Set to 1
Flag contents are read
(1) If the supply voltage rises after the battery has been set, and exceeds VPOC (POC detection voltage), reset is cleared. Because the supply voltage rises from 0 V, which is lower than VID (RAM retention detection voltage), the RAM retention flag remains in the initial status 0. (2) The supply voltage has now risen to the level at which the device can operate. Write the necessary data to the RAM and set the RAM retention flag to 1. (3) The device is reset if the supply voltage drops below VPOC. At point (A) in the figure, the voltage is lower than VID. Consequently, the RAM retention flag is cleared to 0. (4) If the RAM retention flag is checked by software after reset has been cleared, it is 0. This means that the contents of the RAM may have been lost. If this case, initialize the RAM by software. Cautions 1. The software developed for the PD67A, 68A and 69A (using the RAM retention flag) can be used for the PD6P8 as is. 2. Unlike the PD67A, 68A and 69A, the RAM retention detection voltage of the PD6P8 is the same as the POC detection voltage. When software is newly developed, it is not necessary to use the RAM retention flag if only the RAM is initialized by reset.
Data Sheet U17848EJ3V0DS
23
PD6P8, 6P8A, 6P8B
Figure 4-3. Supply Voltage Transition and Detection Voltage (PD6P8A, 6P8B)
VDD
VPOC (A) VID (B)
POC detection voltage (Refer to 8. POC CIRCUIT) VPOC = 1.8 V (TYP.) RAM retention detection voltage VID = 1.6 V (TYP.)
0V (1) RAM retention flag (2) (3) (4) (5) (6)
t
Set to 1
Flag contents are read
Flag contents are read
(1) If the supply voltage rises after the battery has been set, and exceeds VPOC (POC detection voltage), reset is cleared. Because the supply voltage rises from 0 V, which is lower than VID (RAM retention detection voltage), the RAM retention flag remains in the initial status 0. (2) The supply voltage has now risen to the level at which the device can operate. Write the necessary data to the RAM and set the RAM retention flag to 1. (3) The device is reset if the supply voltage drops below VPOC. At point (A) in the above figure, the RAM retention flag remains 1 because the supply voltage is higher than VID at this point. (4) If the RAM retention flag is checked by software after reset has been cleared, it is 1. This means that the contents of the RAM have not been lost. It is therefore not necessary to initialize the RAM by software. (5) The device is reset if the supply voltage drops below VPOC. At point (B) in the figure, the voltage is lower than VID. Consequently, the RAM retention flag is cleared to 0. (6) If the RAM retention flag is checked by software after reset has been cleared, it is 0. This means that the contents of the RAM may have been lost. If this case, initialize the RAM by software.
24
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
4.4 Control Register 1 (P4)
Control register 1 consists of 8 bits. The contents that can be controlled are as shown below. After reset, the register becomes 0010 0110B. Table 4-5. Control Register 1 (P4)
Bit Name b7 -- b6 -- b5 KI b4 S0/S1 b3 S2 b2 S1/LED b1 KI/O mode IN OUT 1 b0 S0 mode OFF IN 0
Pull-down Pull-down STOP release mode Setting 0 1 After reset Fixed to 0 0 Fixed to 0 0 OFF ON 1 OFF ON 0 Disable Enable 0 S1 LED 1
b0: Specifies the input mode of the S0 port. 0 = OFF mode (high impedance); 1 = IN (input mode). b1: Specifies the I/O mode of the KI/O port. 0 = IN (input mode); 1 = OUT (output mode). b2: Specifies the I/O mode of the S1/LED port. 0 = S1 (input mode); 1 = LED (output mode). b3: Specified the use of STOP mode release by S2 port (with/without pull-down resistor). 0 = disable (without pull-down); 1 = enable (with pull-down). b4: Specifies the use of a pull-down resistor in S0/S1 port input mode. 0 = OFF (not used); 1 = ON (used) b5: Specifies the use of a pull-down resistor for the KI port. 0 = OFF (not used); 1 = ON (used). Remark In output mode or in OFF mode, all the pull-down resistors are automatically disconnected.
Data Sheet U17848EJ3V0DS
25
PD6P8, 6P8A, 6P8B
5. TIMER 5.1 Timer Configuration
The timer is the block used for creating a remote control transmission pattern. As shown in Figure 4-1, it consists of a 9-bit down counter (t8 to t0), a flag (t9) permitting the 1-bit timer output, and a zero detector. Figure 5-1. Timer Configuration
T T1 t9 t8 t7 t6 T0 t5 t4 t3 t2 9-bit down counter t1 t0
Count clock
fX/64
S1/LED
Carrier synchronous circuit
Timer operation end signal (HALT # 101B release signal) Zero detector
REM
Carrier signal
26
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
5.2 Timer Operation
The timer starts (counting down) when a value other than 0 is set for the down counter with a timer manipulation instruction. The timer manipulation instructions for making the timer start operation are shown below: MOV T0, A MOV T1, A MOV T, #data10 MOV T, @R0 The down counter is decremented (-1) in the cycle of 64/fX. If the value of the down counter becomes 0, the zero detector generates the timer operation end signal to stop the timer operation. At this time, if the timer is in HALT mode (HALT #x101B) waiting for the timer to stop its operation, the HALT mode is released and the instruction following the HALT instruction is executed. The output of the timer operation end signal is continued while the down counter is 0 and the timer is stopped. The following relational expression applies between the timer's output time and the down counter's set value. Timer output time = (Set value + 1) x 64/fX - 4/fX In addition, when the timer is set successively, the timer output time is also 4/fX shorter than the total time. An example is shown below. Example When fX = 4 MHz MOV T, #3FFH STTS #05H HALT #05H MOV T, #232H STTS #05H HALT #05H In the case above, the timer output time is as follows. (Set value + 1) x 64/fX + (Set value + 1) x 64/fX - 4/fX = (511 + 1) x 64/4 + (50 + 1) x 64/4 - 4/4 = 9.007 ms
Data Sheet U17848EJ3V0DS
27
PD6P8, 6P8A, 6P8B
By setting the flag (t9) that enables the timer output to 1, the timer can output its operation status from the S1/ LED pin and the REM pin. The REM pin can also output the carrier while the timer is in operation. Table 5-1. Timer Output (at t9 = 1)
S1/LED Pin Timer operating Timer halting Low level High level REM Pin High level (or carrier outputNote) Low level
Note The carrier output results if bit 9 (CARY) of the high-level period setting modulo register (MOD1) is cleared (to 0). Figure 5-2. Timer Output (When Carrier Is Not Output)
4/fX LED
Timer output time: (Set value + 1) x 64/fX -- 4/fX
REM
28
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
5.3 Carrier Output
5.3.1 Carrier output generator The carrier generator consists of a 9-bit counter and two modulo registers for setting the high- and low-level periods (MOD1 and MOD0 respectively). Figure 5-3. Configuration of Remote Controller Carrier Generator
M1 M11 Carrier signal M10 0 M01 t8 t7 t6 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 CARY Modulo register for setting the high-level period (MOD1)
M0 M00 t5 t4 t3 t2 t1 t0
Modulo register for setting the low-level period (MOD0)Note 1
Selector
F/F
Match
Comparator
9-bit counter Clear
2fX
Multiplier
fX
t9Note 2 fX
Notes 1. Bit 9 of the modulo register for setting the low-level period (MOD0) is fixed to 0. 2. t9: Flag that enables timer output (timer block) (see Figure 5-1 Timer Configuration) The carrier duty ratio and carrier frequency can be determined by setting the high- and low-level widths using the respective modulo registers. Each of these widths can be set in a range of 250 ns to 64 s (@ fX = 4 MHz). The system clock multiplied by 2 is used for the 9-bit counter input (8 MHz when fX = 4 MHz). MOD0 and MOD1 are read and written using timer manipulation instructions. MOV A, M00 MOV A, M01 MOV A, M10 MOV A, M11 MOV M00, A MOV M01, A MOV M10, A MOV M11, A MOV M0, #data10 MOV M1, #data10 MOV M0, @R0 MOV M1, @R0
The values of MOD0 and MOD1 can be calculated from the following expressions. MOD0 = (2 x fX x (1 - D) x T) - 1 MOD1 = (2 x fX x D x T) - 1 Caution Be sure to input values in range of 001H to 1FFH to MOD0 and MOD1. Remark D: Carrier duty ratio (0 < D < 1) fX: Input clock (MHz) T: Carrier cycle (s)
Data Sheet U17848EJ3V0DS
29
PD6P8, 6P8A, 6P8B
5.3.2 Carrier output control Remote controller carrier can be output from the REM pin by clearing (0) bit 9 (CARY) of the modulo register for setting the high-level period (MOD1). When performing carrier output, be sure to set the timer operation after setting the MOD0 and MOD1 values. Note that a malfunction may occur if the values of MOD0 and MOD1 are changed while carrier is being output from the REM pin. Executing the timer manipulation instruction starts the carrier output from the low level. If the timer's down counter reaches 0 during carrier output, carrier output is stopped and the REM pin becomes low level. If the down counter reaches 0 while the carrier output is high level, carrier output will stop after first becoming low level following the set period of high level. Figure 5-4. Timer Output (When Carrier Is Output)
Timer manipulation instruction Timer output time: (Set value + 1) x 64/fX - 4/fX LED
REM 4/fX tL tH Note
Note If the down counter reaches 0 while the carrier output is high level, carrier output will stop after becoming low level.
30
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
Output from the REM pin is as follows, in accordance with the values set to bit 9 (CARY) of MOD1 and the timer output enable flag (t9), and the value of the timer block's 9-bit down counter (t0 to t8). Table 5-2. REM Pin Output
MOD1 Bit 9 (CARY) -- -- 0 1 Timer Output Enable Flag (Timer Block t9) -- 0 1 9-Bit Down Counter (Timer Block t0 to t8) 0 Other than 0 Carrier outputNote High-level output REM Pin Low-level output
Note Input values in the range of 001H to 1FFH to MOD0 and MOD1. Caution MOD0 and MOD1 must be set while the REM pin is low level (t9 = 0 or t0 to t8 = 0). Table 5-3. Example of Carrier Frequency Settings (fX = 4 MHz)
Setting Value MOD1 01H 07H 13H 27H 41H 41H 45H 45H 45H 47H 48H 69H 77H C7H FFH MOD0 01H 0BH 13H 27H 41H 85H 89H 8BH 8CH 91H 94H D5H 77H C7H FFH 0.25 1.0 2.5 5.0 8.25 8.25 8.75 8.75 8.75 9.0 9.125 13.25 15.0 25.0 32.0 0.25 1.5 2.5 5.0 8.25 16.75 17.25 17.5 17.625 18.25 18.625 26.75 15.0 25.0 32.0 0.5 2.5 5.0 10 16.5 25 26.0 26.25 26.375 27.25 27.75 40.0 30.0 50.0 64.0 2,000 400 200 100 60.6 40 38.5 38.10 37.9 36.7 36.0 25 33.3 20 15.6 1/2 2/5 1/2 1/2 1/2 1/3 1/3 1/3 1/3 1/3 1/3 1/3 1/2 1/2 1/2 tH (s) tL (s) T (s) fC (kHz) Duty
tH
tL
Carrier signal
T
Data Sheet U17848EJ3V0DS
31
PD6P8, 6P8A, 6P8B
5.4 Software Control of Timer Output
The timer output can be controlled by software. As shown in Figure 4-5, a pulse with a minimum width of 64/f X - 4/fX can be output. Figure 5-5. Output of Pulse of 1-Instruction Cycle Width . . . MOV T, #0000000000B; low-level output from the REM pin . . . MOV T, #1000000000B; high-level output from the REM pin MOV T, #0000000000B; low-level output from the REM pin . . .
4/fX 64/fX - 4/fX
LED
REM
32
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
6. STANDBY FUNCTION 6.1 Outline of Standby Function
To save current consumption, two types of standby modes, i.e., HALT mode and STOP mode, have been provided available. In STOP mode, the system clock stops oscillation. At this time, the XIN and XOUT pins are fixed to a low level. In HALT mode, CPU operation halts, while the system clock continues oscillation. When in HALT mode, the timer (including REM output and LED output) operates. In either STOP mode or HALT mode, the statuses of the data memory, accumulator, and port registers, etc. immediately before the standby mode is set are retained. Therefore, make sure to set the port status for the system so that the current consumption of the whole system is suppressed before the standby mode is set. Table 6-1. Statuses During Standby Mode
STOP Mode Setting instruction Clock oscillator CPU Data memory Operation statuses Accumulator Flag F CY Port register Timer HALT instruction Oscillation stopped * Operation halted * Immediately preceding status retained * Immediately preceding status retained * 0 (When 1, the flag is not placed in the standby mode.) * Immediately preceding status retained * Immediately preceding status retained * Operation halted * Operable (The count value is reset to "0") Oscillation continued HALT Mode
Cautions 1. Write the NOP instruction as the first instruction after STOP mode is released. 2. When standby mode is released, the status flag (F) is set (to 1). 3. If, at the point the standby mode has been set, its release condition is met, then the system does not enter the standby mode. However, the status flag (F) is set (1).
Data Sheet U17848EJ3V0DS
33
PD6P8, 6P8A, 6P8B
6.2 Standby Mode Setting and Release
The standby mode is set with the HALT #b3b2b1b0B instruction for both STOP mode and HALT mode. For the standby mode to be set, the status flag (F) is required to have been cleared (to 0). The standby mode is released by the release condition specified with the reset (POC) or the operand of HALT instruction. If the standby mode is released, the status flag (F) is set (to 1). Even when the HALT instruction is executed in the state that the status flag (F) has been set (to 1), the standby mode is not set. If the release condition is not met at this time, the status flag is cleared (to 0). If the release condition is met, the status flag remains set (to 1). Even in the case when the release condition has been already met at the point that the HALT instruction is executed, the standby mode is not set. Here, also, the status flag (F) is set (to 1). Caution Depending on the status of the status flag (F), the HALT instruction may not be executed. Be careful about this. For example, when setting HALT mode after checking the key status with the STTS instruction, the system does not enter HALT mode as long as the status flag (F) remains set (to 1) and thus sometimes performs an unintended operation. In this case, the intended operation can be realized by executing the STTS instruction immediately after setting the timer to clear (to 0) the status flag. Example STTS MOV STTS #03H ;To check the KI pin status. ;To set the timer ;To clear the status flag ;To set HALT mode
...
T, #0xxH #05H
...
HALT
(During this time, be sure not to execute an instruction that may set the status flag.) #05H
Table 6-2. Addresses Executed After Standby Mode Release
Release Condition Reset Release condition shown in Table 5-3 Address Executed After Release Address 0 The address following the HALT instruction
34
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
Table 6-3. Standby Mode Setup (HALT #b3b2b1b0B) and Release Conditions
Operand Value of HALT Instruction b3 0 b2 0 0 1 1 b1 0 1 1 b0 0 1 0 STOP STOP STOPNote 1 STOP All KI/O pins are high-level output. All KI/O pins are high-level output. The KI/O0 pin is high-level output. High level is input to at least one of KI pins. High level is input to at least one of KI pins. High level is input to at least one of KI pins.
Setting Mode
Precondition for Setup
Release Condition
Any of the combinations of b2b1b0 above
[The following condition is added in addition to the above.] -- High level is input to at least one of S0, S1 and S2 pinsNote 2.
0/1
1
0
1
HALT
--
When the timer's down counter is 0
Notes 1. When setting HALT #x110B, configure a key matrix by using the KI/O0 pin and the KI pin so that the standby mode can be released. 2. At least one of the S0, S1 and S2 pins (the pin used for releasing the standby mode) must be specified as follows: S0, S1 pins: S2 pin: Input mode (specified by bits 0 and 2 of the P4 register) Use of STOP mode release enabled (specified by bit 3 of the P4 register)
Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value other than that above or when the precondition has not been satisfied when executing the HALT instruction. 2. If STOP mode is set when the timer's down counter is not 0 (timer operating), the system is placed in STOP mode only after all the 10 bits of the timer's down counter and the timer output permit flag are cleared to 0. 3. Write the NOP instruction as the first instruction after STOP mode is released.
Data Sheet U17848EJ3V0DS
35
PD6P8, 6P8A, 6P8B
6.3 Standby Mode Release Timing
(1) STOP mode release timing Figure 6-1. STOP Mode Release by Release Condition
Wait (52/fX + )
HALT instruction (STOP mode) Standby release signal Operation mode STOP mode Oscillation stopped
HALT mode
Operation mode
Oscillation Clock
Oscillation : Oscillation growth time
Caution When a release condition is met in the STOP mode, the device is released from the STOP mode, and goes into a wait state. At this time, if the release condition is not held, the device goes into STOP mode again after the wait time has elapsed. Therefore, when releasing the STOP mode, it is necessary to hold the release condition longer than the wait time. (2) HALT mode release timing Figure 6-2. HALT Mode Release by Release Condition
Standby release signal
HALT instruction (HALT mode) Operation mode
HALT mode
Operation mode
Oscillation Clock
36
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
7. RESET
A system reset is effected by the following causes: * When the POC circuit has detected low power-supply voltage * When the operand value is illegal or does not satisfy the precondition when the HALT instruction is executed * When the accumulator is 0H when the RLZ instruction is executed * When stack pointer overflows or underflows Table 7-1. Hardware Statuses After Reset
* Reset by On-Chip POC Circuit During Operation * Reset by the On-Chip POC Circuit During * Reset by Other FactorsNote 1 Standby Mode 000H 0B R0 = DP 000H
Hardware PC (11 bits) SP (1 bit) Data memory
R1 to RF Undefined Undefined 0B 0B 000H P0 P1 FFH xxxx 11x1BNote 2 0000x000BNote 3 26H
Accumulator (A) Status flag (F) Carry flag (CY) Timer (10 bits) Port register
Control register P3 P4
Notes 1. The following resets are available. * Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy the precondition) * Reset when executing the RLZ instruction (when A = 0) * Reset by stack pointer's overflow or underflow 2. x: Refers to the value by the KI or S2 pin status. In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when POC is released by supply voltage rising (Can be left open. When open, leave the pull-down resistor connected). 3. x: Refers to the value based on a decrease of power supply voltage (0 when VDD VID). Remark VID: RAM retention detection voltage
Data Sheet U17848EJ3V0DS
37
PD6P8, 6P8A, 6P8B
8. POC CIRCUIT
The POC circuit monitors the power supply voltage and applies an internal reset to the microcontroller when the battery is replaced. Cautions 1. There are cases in which the POC circuit cannot detect a low power supply voltage of less than 1 ms. Therefore, if the power supply voltage has become low for a period of less than 1 ms, the POC circuit may malfunction because it does not generate an internal reset signal. 2. Clock oscillation is stopped by the resonator due to low power supply voltage before the POC circuit generates the internal reset signal. In this case, malfunction may result when the power supply voltage is recovered after the oscillation is stopped. This type of phenomenon takes place because the POC circuit does not generate an internal reset signal (because the power supply voltage recovers before the low power supply voltage is detected) even though the clock has stopped. If, by any chance, a malfunction has taken place, remove the battery for a short time and put it back. In most cases, normal operation will be resumed. 3. In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when POC is released due to supply voltage rising (Can be left open. When open, leave the pull-down resistor connected).
38
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
8.1 Functions of POC Circuit
The POC circuit has the following functions: * Generates an internal reset signal when VDD VPOC. * Cancels an internal reset signal when VDD > VPOC. Here, VDD: power supply voltage, VPOC: POC detection voltage.
VDD 3.6 V Clock frequency fX = 3.5 to 4.5 MHz 1.9 V VPOC Approx. 1.7 V POC detection voltage VPOC = 1.8 V (TYP.)Note 3 Operating ambient temperature TA = - 40 to + 85C
0V
t
Internal reset signal Operation mode
Reset
Note 1
Reset Note 2
Notes 1. Actually, oscillation stabilization wait time must elapse before the circuit is switched to operation mode. The oscillation stabilization wait time is about 534/fX to 918/fX (when about 134 to 230 s; @ fX = 4 MHz). 2. For the POC circuit to generate an internal reset signal when the power supply voltage has fallen, it is necessary for the power supply voltage to be kept less than the VPOC for the period of 1 ms or more. Therefore, in reality, there is the time lag of up to 1 ms until the reset takes effect. 3. The POC detection voltage (VPOC) varies between approximately 1.7 to 1.9 V; thus, the reset may be canceled at a power supply voltage smaller than the guaranteed range (VDD = 1.9 to 3.6 V). However, as long as the conditions for operating the POC circuit are met, the actual lowest operating power supply voltage becomes lower than the POC detection voltage. Therefore, there is no malfunction occurring due to a shortage of power supply voltage. However, malfunction for such reasons as the clock not oscillating due to low power supply voltage may occur (refer to Cautions 3 in 8 POC CIRCUIT).
8.2 Oscillation Check at Low Supply Voltage
A reliable reset operation can be expected of the POC circuit if it satisfies the condition that the clock can oscillate even at low power supply voltage (the oscillation start voltage of the resonator being even lower than the POC detection voltage). Whether this condition is met or not can be checked by measuring the oscillation status in a product that actually includes a POC circuit, as follows. <1> Connect a storage oscilloscope to the XOUT pin so that the oscillation status can be measured. <2> Connect a power supply whose output voltage can be varied and then gradually raise the power supply voltage VDD from 0 V (making sure to avoid VDD > 3.6V). At first (during VDD < approx. 1.7 V), the XOUT pin is 0 V regardless of the VDD. However, at the point that VDD reaches the POC detection voltage (VPOC = 1.8 V (TYP.)), the voltage of the XOUT pin jumps to about 0.5VDD. Maintain this power supply voltage for a while to measure the waveform of the XOUT pin. If by any chance the oscillation start voltage of the resonator is lower than the POC detection voltage, the growing oscillation of the XOUT pin can be confirmed within several ms after the VDD has reached the VPOC.
Data Sheet U17848EJ3V0DS
39
PD6P8, 6P8A, 6P8B
9. SYSTEM CLOCK OSCILLATOR (PD6P8, 6P8A)
The system clock oscillator consists of oscillators for ceramic resonators (fX = 3.5 to 4.5 MHz). Figure 9-1. System Clock
XOUT
XIN
GND
Ceramic resonator
The system clock oscillator stops oscillating when a reset is applied or in STOP mode. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as GND. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator.
40
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
10. INSTRUCTION SET 10.1 Machine Language Output by Assembler
The bit length of the machine language of this product is 10 bits per word. However, the machine language that is output by the assembler is extended to 16 bits per word. As shown in the example below, the extension is made by inserting 3-bit extended bits (111) in two locations. Figure 10-1. Example of Assembler Output (10 Bits Extended to 16 Bits) <1> In the case of "ANL A, @R0H"
1
1010
1
0000
111
1
1010
111
1
0000
= FAF0
Extended bits
Extended bits
<2> In the case of "OUT P0, #data8"
0
0110
1
1000
111
0
0110
111
1
1000
= E6F8
Extended bits
Extended bits
Data Sheet U17848EJ3V0DS
41
PD6P8, 6P8A, 6P8B
10.2 Circuit Symbol Description
A: ASR: addr: CY: data4: data8: data10: F: M0: M00: M01: M1: M10: M11: PC: Pn: P0n: P1n: ROMn: Rn: R0n: R1n: SP: T: T0: T1: (x): Accumulator Address stack register Program memory address Carry flag 4-bit immediate data 8-bit immediate data 10-bit immediate data Status flag Modulo register for setting the low-level period Modulo register for setting the low-level period (lower 4 bits) Modulo register for setting the low-level period (higher 4 bits) Modulo register for setting the high-level period Modulo register for setting the high-level period (lower 4 bits) Modulo register for setting the high-level period (higher 4 bits) Program Counter Port register pair (n = 0, 1, 3, 4) Port register (lower 4 bits) Port register (higher 4 bits) Bit n of the program memory's (n = 0 to 9) Register pair Data memory (General-purpose register; n = 0 to F) Data memory (General-purpose register; n = 0 to F) Stack Pointer Timer register Timer register (lower 4 bits) Timer register (higher 4 bits) Content addressed with x
42
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
10.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table
Accumulator Operation Instructions
Instruction Code 1st Word ANL A, R0n A, R1n A, @R0H FBEn FAEn FAF0 2nd Word 3rd Word CY A3 * Rmn3 CY A3 * ROM7 A, @R0L FBF0 CY A3 * ROM3 A, #data4 FBF1 data4 CY A3 * data43 ORL A, R0n A, R1n A, @R0H FDEn FCEn FCF0 (A) (A) (Rmn) m = 0, 1 n = 0 to F CY 0 (A) (A) ((P13), (R0))7-4 CY 0 A, @R0L FDF0 (A) (A) ((P13), (R0))3-0 CY 0 A, #data4 FDF1 data4 (A) (A) data4 CY 0 XRL A, R0n A, R1n A, @R0H F5En F4En F4F0 (A) (A) (Rmn) m = 0, 1 n = 0 to F CY A3 * Rmn3 (A) (A) ((P13), (R0))7-4 CY A3 * ROM7 A, @R0L F5F0 (A) (A) ((P13), (R0))3-0 CY A3 * ROM3 A, #data4 F5F1 data4 (A) (A) data4 CY A3 * data43 INC A F4F3 (A) (A) + 1 if (A) = 0 CY 1 else CY 1 RL A FCF3 (An+1) (An), (A0) (A3) CY A3 RLZ A FEF3 if A = 0 CY A3 reset else (An+1) (An), (A0) (A3) 1 2 1 2 1 Instruction Length Instruction Cycle 1
Mnemonic
Operand
Operation
Data Sheet U17848EJ3V0DS
(A) (A)
(A) (A)
(A) (A)
(A) (A)
(Rmn) m = 0, 1 n = 0 to F
1
((P13), (R0))7-4
((P13), (R0))3-0
data4
2
43
PD6P8, 6P8A, 6P8B
I/O Instructions
Instruction Code 1st Word IN A, P0n A, P1n OUT P0n, A P1n, A ANL A, P0n A, P1n ORL A, P0n A, P1n XRL A, P0n A, P1n FFF8 + n FEF8 + n E5F8 + n E4F8 + n FBF8 + n FAF8 + n FDF8 + n FCF8 + n F5F8 + n F4F8 + n 2nd Word -- -- -- -- -- -- -- -- -- -- 3rd Word -- -- -- -- -- -- -- -- -- -- (A) (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY A3 * Pmn3 (A) (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY 0 (A) (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY A3 * Pmn3 Instruction Length (Pn) data8 n = 0, 1, 3, 4 2 1 Instruction Cycle (A) (Pmn) CY 0 (Pmn) (A) m = 0, 1 n = 0, 1, 3, 4 m = 0, 1 n = 0, 1, 3, 4 1 Instruction Length 1 Instruction Cycle
Mnemonic
Operand
Operation
Mnemonic OUT
Operand
Instruction Code 1st Word 2nd Word data8 3rd Word
Pn, #data8 E6F8 + n
Remark
Pn: P1n to P0n are dealt with in pairs.
Data Transfer Instruction
Instruction Code 1st Word MOV A, R0n A, R1n A, @R0H FFEn FEEn FEF0 2nd Word 3rd Word (A) (Rmn) CY 0 (A) ((P13), (R0))7-4 CY 0 A, @R0L FFF0 (A) ((P13), (R0))3-0 CY 0 A, #data4 R0n, A R1n, A FFF1 E5En E4En data4 (A) data4 CY 0 (Rmn) (A) m = 0, 1 n = 0 to F 2 1 m = 0, 1 n = 0 to F 1 Instruction Length 1 Instruction Cycle
Mnemonic
Operand
Mnemonic MOV
Operand Rn, #data8 E6En Rn, @R0 E7En
Instruction Code 1st Word 2nd Word data8 -- 3rd Word -- --
(R1n to R0n) data8
(R1n to R0n) ((P13), (R0))n = 1 to F
Remark
Rn: R1n to R0n are handled in pairs.
44
Data Sheet U17848EJ3V0DS
Operation
Operation
Operation n = 0 to F
Instruction Length 2 1
Instruction Cycle 1
PD6P8, 6P8A, 6P8B
Branch Instructions
Instruction Code 1st Word JMP addr (Page 0) E8F1 addr (Page 1) E9F1 addr (Page 2) E8F4 addr (Page 3) E9F4 JC addr (Page 0) ECF1 addr (Page 1) EAF1 addr (Page 2) ECF4 addr (Page 3) EAF4 JNC addr (Page 0) EDF1 addr (Page 1) EBF1 addr (Page 2) EDF4 addr (Page 3) EBF4 JF addr (Page 0) EEF1 addr (Page 1) F0F1 addr (Page 2) EEF4 addr (Page 3) F0F4 JNF addr (Page 0) EFF1 addr (Page 1) F1F1 addr (Page 2) EFF4 addr (Page 3) F1F4 2nd Word addr addr addr addr addr addr addr addr addr addr addr addr addr addr addr addr addr addr addr addr if F = 0 PC addr else PC PC + 2 if F = 1 PC addr else PC PC + 2 if CY = 0 PC addr else PC PC + 2 if CY = 1 PC addr else PC PC + 2 3rd Word PC addr 2 Instruction Length 1 Instruction Cycle
Mnemonic
Operand
Operation
Caution 0 and 4, which refer to PAGE0 and 4, are not written when describing mnemonics. Subroutine Instructions
Instruction Code 1st Word CALL addr (Page 0) E6F2 addr (Page 1) E6F2 addr (Page 2) E6F2 addr (Page 3) E6F2 RET E8F2 2nd Word E8F1 E9F1 E8F4 E9F4 3rd Word addr addr addr addr PC ASR, SP SP - 1 1 1 SP SP + 1, ASR PC, PC addr 3 Instruction Length 2 Instruction Cycle
Mnemonic
Operand
Operation
Caution 0 and 4, which refer to PAGE0 and 4, are not written when describing mnemonics.
Data Sheet U17848EJ3V0DS
45
PD6P8, 6P8A, 6P8B
Timer Operation Instructions
Instruction Code 1st Word MOV A, T0 A, T1 A, M00 A, M01 A, M10 A, M11 T0, A T1, A M00, A M01, A M10, A M11, A FFFF FEFF FFF6 FEF6 FFF7 FEF7 E5FF F4FF E5F6 E4F6 E5F7 E4F7 2nd Word 3rd Word (A) (Tn) CY 0 (A) (M0n) CY 0 (A) (M1n) CY 0 (Tn) (A) (T) n 0 (M0n) (A) CY 0 (M1n) (A) CY 0 Instruction Code 1st Word MOV T, #data10 M0, #data10 M1, #data10 T, @R0 M0, @R0 M1, @R0 E6FF E6F6 E6F7 F4FF E7F6 E7F7 2nd Word data10 data10 data10 3rd Word (T) data10 (M0) data10 (M1) data10 (T) ((P13), (R0)) (M0) ((P13), (R0)) (M1) ((P13), (R0)) 1 2 Instruction Length 1 Instruction Cycle n = 0, 1 n = 0, 1 n = 0, 1 n = 0, 1 n = 0, 1 n = 0, 1 1 Instruction Length 1 Instruction Cycle
Mnemonic
Operand
Operation
Mnemonic
Operand
Operation
Others
Instruction Code 1st Word HALT STTS #data4 #data4 E2F1 E3F1 2nd Word data4 data4 3rd Word Standby mode if statuses match else R0n E3En F0 F1 n = 0 to F CY 1 1 F0 CY 0 F1 2 Instruction Length 1 Instruction Cycle
Mnemonic
Operand
Operation
if statuses match else
SCAF
FAF3
if A = 0FH else
NOP
E0E0
PC PC + 1
46
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
10.4 Accumulator Manipulation Instructions
ANL A, R0n ANL A, R1n <1> Instruction code: <2> Cycle count: <3> Function:
1 1 0 1 R4 0 R3 R2 R1 R0
1 CY A3 * Rmn3
(A) (A)
(Rmn)
m = 0, 1
n = 0 to F
The accumulator contents and the register Rmn contents are ANDed and the results are entered in the accumulator. ANL A, @R0H ANL A, @R0L <1> Instruction code: <2> Cycle count: <3> Function:
1 1 0 1 0/1 1 0 0 0 0
1 CY A3 * ROM7 CY A3 * ROM3

(A) (A) (A) (A)
((P13), (R0))7-4 (in the case of ANL A, @R0H) ((P13), (R0))3-0 (in the case of ANL A, @R0L)
The accumulator contents and the program memory contents specified by the control register P13 and register pair R10 to R00 are ANDed and the results are entered in the accumulator. If H is specified, b7, b6, b5 and b4 take effect. If L is specified, b3, b2, b1 and b0 take effect. * Program memory (ROM) organization
b9
b7
b6
b5
b4
b8
b3
b2
b1
b0
H
L
Valid bits at the time of accumulator manipulation
ANL A, #data4 <1> Instruction code: <2> Cycle count: <3> Function:
1 101110001 0 0 0 0 0 0 d3 d2 d1 d0
1 CY A3 * data43
(A) (A)
data4
The accumulator contents and the immediate data are ANDed and the results are entered in the accumulator.
Data Sheet U17848EJ3V0DS
47
PD6P8, 6P8A, 6P8B
ORL A, R0n ORL A, R1n <1> Instruction code: <2> Cycle count: <3> Function:
1 1 1 0 R4 0 R3 R2 R1 R0
1 (A) (A) (Rmn) CY 0 m = 0, 1 n = 0 to F
The accumulator contents and the register Rmn contents are ORed and the results are entered in the accumulator. ORL A, @R0H ORL A, @R0L <1> Instruction code: <2> Cycle count: <3> Function:
1 1 1 0 0/1 1 0 0 0 0
1 (A) (A) (P13), (R0))7-4 (in the case of ORL A, @R0H) (A) (A) (P13), (R0))3-0 (in the case of ORL A, @R0L) CY 0
The accumulator contents and the program memory contents specified by the control register P13 and register pair R10-R00 are ORed and the results are entered in the accumulator. If H is specified, b7, b6, b5 and b4 take effect. If L is specified, b3, b2, b1 and b0 take effect. ORL A, #data4 <1> Instruction code: <2> Cycle count: <3> Function:
1 110110001 0 0 0 0 0 0 d3 d2 d1 d0
1 (A) (A) data4 CY 0
The accumulator contents and the immediate data are exclusive-ORed and the results are entered in the accumulator. XRL A, R0n XRL A, R1n <1> Instruction code: <2> Cycle count: <3> Function:
1 0 1 0 R4 0 R3 R2 R1 R0
1 (A) (A) (Rmn) CY A3 * Rmn3 m = 0, 1 n = 0 to F
The accumulator contents and the register Rmn contents are ORed and the results are entered in the accumulator.
48
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
XRL A, @R0H XRL A, @R0L <1> Instruction code: <2> Cycle count: <3> Function:
1 0 1 0 0/1 1 0 0 0 0
1 (A) (A) (P13), (R0))7-4 (in the case of XRL A, @R0H) CY A3 * ROM7 (A) (A) (P13), (R0))3-0 (in the case of XRL A, @R0L) CY A3 * ROM3
The accumulator contents and the program memory contents specified by the control register P13 and register pair R10-R00 are exclusive-ORed and the results are entered in the accumulator. If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b0 take effect. XRL A, #data4 <1> Instruction code: <2> Cycle count: <3> Function:
1 010110001 0 0 0 0 0 0 d3 d2 d1 d0
1 (A) (A) data4 CY A3 * data43
The accumulator contents and the immediate data are exclusive-ORed and the results are entered in the accumulator. INC A <1> Instruction code: <2> Cycle count: <3> Function:
1 010010011
1 (A) (A) + 1 if A=0 CY 1 else CY 0
The accumulator contents are incremented (+1). RL A <1> Instruction code: <2> Cycle count: <3> Function:
1 110010011
1 (An + 1) (An), (A0) (A3) CY A3
The accumulator contents are rotated anticlockwise bit by bit. RLZ A <1> Instruction code: <2> Cycle count: <3> Function:
1 111010011
1 if A=0 reset else (An + 1) (An), (A0) (A3)
CY A3 The accumulator contents are rotated anticlockwise bit by bit. If A = 0H at the time of command execution, an internal reset takes effect.
Data Sheet U17848EJ3V0DS
49
PD6P8, 6P8A, 6P8B
10.5 I/O Instructions
IN A, P0n IN A, P1n <1> Instruction code: <2> Cycle count: <3> Function:
1 1 1 1 P4 1 1 P2 P1 P0
1 (A) (Pmn) CY 0 m = 0, 1 n = 0, 1, 3, 4
The port Pmn data is loaded (read) onto the accumulator. OUT P0n, A OUT P1n, A <1> Instruction code: <2> Cycle count: <3> Function:
0 0 1 0 P4 1 1 P2 P1 P0
1 (Pmn) (A) m = 0, 1 n = 0, 1, 3, 4
The accumulator contents are transferred to port Pmn to be latched. ANL A, P0n ANL A, P1n <1> Instruction code: <2> Cycle count: <3> Function:
1 1 0 1 P4 1 1 P2 P1 P0
1 CY A3 * Pmn
(A) (A)
(Pmn)
m = 0, 1
n = 0, 1, 3, 4
The accumulator contents and the port Pmn contents are ANDed and the results are entered in the accumulator. ORL A, P0n ORL A, P1n <1> Instruction code: <2> Cycle count: <3> Function:
1 1 1 0 P4 1 1 P2 P1 P0
1 (A) (A) (Pmn) CY 0 m = 0, 1 n = 0, 1, 3, 4
The accumulator contents and the port Pmn contents are ORed and the results are entered in the accumulator. XRL A, P0n XRL A, P1n <1> Instruction code: <2> Cycle count: <3> Function:
1 0 1 0 P4 1 1 P2 P1 P0
1 (A) (A) (Pmn) CY A3 * Pmn m = 0, 1 n = 0, 1, 3, 4
The accumulator contents and the port Pmn contents are exclusive-ORed and the results are entered in the accumulator.
50
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
OUT Pn, #data8 <1> Instruction code: : <2> Cycle count: <3> Function:
0 0 1 1 0 1 1 P2 P1 P0 0 d7 d6 d5 d4 0 d3 d2 d1 d0
1 (Pn) data8 n = 0, 1, 3, 4
The immediate data is transferred to port Pn. In this case, port Pn refers to P1n to P0n operating in pairs.
10.6 Data Transfer Instructions
MOV A, R0n MOV A, R1n <1> Instruction code: <2> Cycle count: <3> Function:
1 1 1 1 R4 0 R3 R2 R1 R0
1 (A) (Rmn) CY 0 m = 0, 1 n = 0 to F
The register Rmn contents are transferred to the accumulator. MOV A, @R0H <1> Instruction code: <2> Cycle count: <3> Function:
1 111010000
1 (A) ((P13), (R0))7-4 CY 0
The higher 4 bits (b7 b6 b5 b4) of the program memory specified by control register P13 and register pair R10-R00 are transferred to the accumulator. b9 is ignored. MOV A, @R0L <1> Instruction code: <2> Cycle count: <3> Function:
1 111110000
1 (A) ((P13), (R0))3-0 CY 0
The lower 4 bits (b3 b2 b1 b0) of the program memory specified by control register P13 and register pair R10 to R00 are transferred to the accumulator. b8 is ignored. * Program memory (ROM) contents
@R0 H b9 b7 b6 b5 b4 b8 b3
@R0 L b2 b1 b0
MOV A, #data4 <1> Instruction code: : <2> Cycle count: <3> Function:
1 111110001 0 0 0 0 0 0 d3 d2 d1 d0
1 (A) data4 CY 0
The immediate data is transferred to the accumulator.
Data Sheet U17848EJ3V0DS
51
PD6P8, 6P8A, 6P8B
MOV R0n, A MOV R1n, A <1> Instruction code: <2> Cycle count: <3> Function:
0 0 1 0 R4 0 R3 R2 R1 R0
1 (Rmn) (A) m = 0, 1 n = 0 to F
The accumulator contents are transferred to register Rmn. MOV Rn, #data8 <1> Instruction code: : <2> Cycle count: <3> Function: pairs. The pair combinations are as follows: R0: R10 - R00 R1: R11 - R01 : RE: R1E - R0E RF: R1F - R0F Lower column Higher column MOV Rn, @R0 <1> Instruction code: <2> Cycle count: <3> Function:
0 0 1 1 1 0 R3 R2 R1 R0 0 0 1 1 0 0 R3 R2 R1 R0 0 d7 d6 d5 d4 0 d3 d2 d1 d0
1 (R1n-R0n) data8 n = 0 to F
The immediate data is transferred to the register. Using this instruction, registers operate as register
1 (R1n-R0n) ((P13), R0)) n = 1 to F
The program memory contents specified by control register P13 and register pair R10 to R00 are transferred to register pair R1n to R0n. The program memory consists of 10 bits and has the following state after the transfer to the register.
Program memory b9 b7 b6 b5 b4 @R0 b8 b3 b2 b1 b0
b9
b7
b6
b5
b4
b8
b3
b2
b1
b0
R1n
R0n
The higher 2 to 4 bits of the program memory address are specified by the control register (P13).
52
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
10.7 Branch Instructions
The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as follows.
PD6P8, 6P8A, 6P8B (ROM: 2K steps): Pages 0, 1
JMP addr <1> Instruction code: Page 0 Page 2 <2> Cycle count: <3> Function: a0). JC addr <1> Instruction code: Page 0 Page 2 <2> Cycle count: <3> Function: 1 if CY = 1 PC addr else PC PC + 2
0110010001 0110010100 0100010001 0100010100
; page 1 ; page 3
0100110001 0100110100
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
1 PC addr
The 10 bits (PC9-0) of the program counter are replaced directly by the specified address addr (a9 to
; page 1 ; page 3
0101010001 0101010100
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
If the carry flag CY is set (to 1), a jump is made to the address specified by addr (a9 to a0). JNC addr <1> Instruction code: Page 0 Page 2 <2> Cycle count: <3> Function: 1 if CY = 0 PC addr else PC PC + 2
0110110001 0110110100
; page 1 ; page 3
0101110001 0101110100
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
If the carry flag CY is cleared (to 0), a jump is made to the address specified by addr (a9 to a0). JF addr <1> Instruction code: Page 0 Page 2 <2> Cycle count: <3> Function: 1 if F=1 PC addr else PC PC + 2
0111010001 0111010100
; page 1 ; page 3
1000010001 1000010100
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
If the status flag F is set (to 1), a jump is made to the address specified by addr (a9 to a0).
Data Sheet U17848EJ3V0DS
53
PD6P8, 6P8A, 6P8B
JNF addr <1> Instruction code: Page 0 Page 2 <2> Cycle count: <3> Function: 1 if F=0 PC addr else PC PC + 2
0111110001 0111110100
; page 1 ; page 3
1000110001 1000110100
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
If the status flag F is cleared (to 0), a jump is made to the address specified by addr (a9 to a0).
10.8 Subroutine Instructions
The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as follows.
PD6P8, 6P8A, 6P8B (ROM: 2K steps): Pages 0, 1
CALL addr <1> Instruction code:
0 011010010
Page 0 Page 2 <2> Cycle count: <3> Function: 2
0100010001 0100010100
; page 1 ; page 3
0100110001 0100110100
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
SP SP + 1 ASR PC PC addr
Increments (+1) the stack pointer value and saves the program counter value in the address stack register. Then, enters the address specified by the operand addr (a9 to a0) into the program counter. If a carry is generated when the stack pointer value is incremented (+1), an internal reset takes effect. RET <1> Instruction code: <2> Cycle count: <3> Function:
0 100010010
1 PC ASR SP SP - 1
Restores the value saved in the address stack register to the program counter. Then, decrements (-1) the stack pointer. If a borrow is generated when the stack pointer value is decremented (-1), an internal reset takes effect.
54
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
10.9 Timer Operation Instructions
MOV A, T0 MOV A, T1 <1> Instruction code: <2> Cycle count: <3> Function:
1 1 1 1 0/1 1 1 1 1 1
1 (A) (Tn) CY 0 n = 0, 1
The timer register Tn contents are transferred to the accumulator. T1 corresponds to (t9, t8, t7, t6); T0 corresponds to (t5, t4, t3, t2).
T t9 t8 T1 t7 t6 t5 t4 T0 t3 t2 t1 t0
MOV T, #data10 Can be set with MOV T, @R0
MOV A, M00 MOV A, M01 <1> Instruction code: <2> Cycle count: <3> Function:
1 1 1 1 0/1 1 0 1 1 0
1 (A) (M0n) CY 0 n = 0, 1
The modulo register M0n contents are transferred to the accumulator. M01 corresponds to (t9, t8, t7, t6); M00 corresponds to (t5, t4, t3, t2).
M0 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0
M01
MOV M0, #data10 Can be set with MOV M0, @R0
M00
Data Sheet U17848EJ3V0DS
55
PD6P8, 6P8A, 6P8B
MOV A, M10 MOV A, M11 <1> Instruction code: <2> Cycle count: <3> Function:
1 1 1 1 0/1 1 0 1 1 1
1 (A) (M1n) CY 0 n = 0, 1
The modulo register M1n contents are transferred to the accumulator. M11 corresponds to (t9, t8, t7, t6); M10 corresponds to (t5, t4, t3, t2).
M1 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0
M11
MOV M1, #data10 Can be set with MOV M1, @R0
M10
MOV T0, A MOV T1, A <1> Instruction code: <2> Cycle count: <3> Function:
0 0 1 0 0/1 1 1 1 1 1
1 (Tn) (A) n = 0, 1
The accumulator contents are transferred to the timer register Tn. T1 corresponds to (t9, t8, t7, t6); T0 corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to T1, t1 becomes 0; if data is transferred to T0, t0 becomes 0. MOV M00, A MOV M01, A <1> Instruction code: <2> Cycle count: <3> Function:
0 0 1 0 0/1 1 0 1 1 0
1 (M0n) (A) CY 0 n = 0, 1
The accumulator contents are transferred to the modulo register M0n. M01 corresponds to (t9, t8, t7, t6); M00 corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to M01, t1 becomes 0; if data is transferred to M00, t0 becomes 0. MOV M10, A MOV M11, A <1> Instruction code: <2> Cycle count: <3> Function:
0 0 1 0 0/1 1 0 1 1 1
1 (M1n) (A) CY 0 n = 0, 1
The accumulator contents are transferred to the modulo register M1n. M11 corresponds to (t9, t8, t7, t6); M10 corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to M11, t1 becomes 0; if data is transferred to M10, t0 becomes 0.
56
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
MOV T, #data10 <1> Instruction code: <2> Cycle count: <3> Function:
0 011011111 t1 t9 t8 t7 t6 t0 t5 t4 t3 t2
1 (T) data10
The immediate data is transferred to the timer register T (t9 to t0). Remark The timer time is set as follows. (Set value + 1) x 64/fX - 4/fX MOV M0, #data10 <1> Instruction code: <2> Cycle count: <3> Function:
0 011010110 t1 t9 t8 t7 t6 t0 t5 t4 t3 t2
1 (M0) data10
The immediate data is transferred to the modulo register M0 (t9 to t0). MOV M1, #data10 <1> Instruction code: <2> Cycle count: <3> Function:
0 011010111 t1 t9 t8 t7 t6 t0 t5 t4 t3 t2
1 (M1) data10
The immediate data is transferred to the modulo register M1 (t9 to t0). MOV T, @R0 <1> Instruction code: <2> Cycle count: <3> Function:
0 011111111
1 (T) ((P13), (R0))
Transfers the program memory contents to the timer register T (t9 to t0) specified by the control register P13 and the register pair R10 to R00. The program memory, which consists of 10 bits, is placed in the following state after the transfer to the register.
Program memory t1 t9 t8 t7 t6 @R0 t0 t5 t4 t3 t2
Timer T
t9
t8 T1
t7
t6
t5
t4 T0
t3
t2
t1
t0
The higher 2 to 4 bits of the program memory address are specified by the control register (P13). Caution When setting a timer value in the program memory, be sure to use the DT quasi-directive.
Data Sheet U17848EJ3V0DS
57
PD6P8, 6P8A, 6P8B
MOV M0, @R0 <1> Instruction code: <2> Cycle count: <3> Function:
0 011110110
1 (M0) ((P13), (R0))
Transfers the program memory contents to the modulo register M0 (t9 to t0) specified by the control register P13 and the register pair R10 to R00. The program memory, which consists of 10 bits, is placed in the following state after the transfer to the register.
Program memory t1 t9 t8 t7 t6 @R0 t0 t5 t4 t3 t2
Modulo register M0
t9
t8
t7
t6
t5
t4
t3
t2
t1
t0
M01
M00
The higher 2 to 4 bits of the program memory address are specified by the control register (P13). Caution When setting a timer value in the program memory, be sure to use the DT quasi-directive. MOV M1, @R0 <1> Instruction code: <2> Cycle count: <3> Function:
0 011110111
1 (M1) ((P13), (R0))
Transfers the program memory contents to the modulo register M1 (t9 to t0) specified by the control register P13 and the register pair R10 to R00. The program memory, which consists of 10 bits, is placed in the following state after the transfer to the register.
Program memory t1 t9 t8 t7 t6 @R0 t0 t5 t4 t3 t2
Modulo register M1
t9
t8
t7
t6
t5
t4
t3
t2
t1
t0
M11
M10
The higher 2 to 4 bits of the program memory address are specified by the control register (P13). Caution When setting a timer value in the program memory, be sure to use the DT quasi-directive.
10.10 Others
HALT #data4 <1> Instruction code: : <2> Cycle count: <3> Function:
0 001010001 0 0 0 0 0 0 d3 d2 d1 d0
1 Standby mode
Places the CPU in standby mode. The condition for having the standby mode (HALT/STOP mode) canceled is specified by the immediate data.
58
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
STTS R0n <1> Instruction code: <2> Cycle count: <3> Function:
0 0 0 1 1 0 R3 R2 R1 R0
1 if statuses match else F0 F1 n = 0 to F
Compares the S0, S1, KI/O, KI, and TIMER statuses with the register R0n contents. If at least one of the statuses matches the bits that have been set, the status flag F is set (to 1). If none of them match, the status flag F is cleared (to 0). STTS #data4 <1> Instruction code: : <2> Cycle count: <3> Function:
0 001110001 0 0 0 0 0 0 d3 d2 d1 d0
1 if statuses match else F0 F1
Compares the S0, S1, S2, KI/O, KI, and TIMER statuses with the immediate data contents. If at least one of the statuses matches the bits that have been set, the status flag F is set (to 1). If none of them match, the status flag F is cleared (to 0). SCAF (Set Carry If ACC = FH) <1> Instruction code: <2> Cycle count: <3> Function:
1 101010011
1 if A = 0FH CY 1 else CY 0
Sets the carry flag CY (to 1) if the accumulator contents are FH. The accumulator values after executing the SCAF instruction are as follows:
Accumulator Value Before Execution xxx0 xx01 x011 0111 1111 After Execution 0000 0001 0011 0111 1111 0 (clear) 0 (clear) 0 (clear) 0 (clear) 1 (set) Carry Flag
Remark NOP
x: don't care
<1> Instruction code: <2> Cycle count: <3> Function: No operation
0 000000000
1 PC PC + 1
Data Sheet U17848EJ3V0DS
59
PD6P8, 6P8A, 6P8B
11. ASSEMBLER RESERVED WORDS 11.1 Mask Option Directives
When creating a program in the PD6P8, 6P8A, 6P8B, it is necessary to use a mask option quasi-directive in the assembler's source program. To create a program for the PD6P8, 6P8A, or 6P8B, a mask option pseudo instruction must be used in the assembler source program, but since the PD6P8, 6P8A, or 6P8B does not have a mask option, describe NOUSECAP. 11.1.1 OPTION and ENDOP quasi-directives The quasi-directives from the OPTION quasi-directive down to the ENDOP quasi-directive are called the mask option definition block. The format of the mask option definition block is as follows: Format Symbol field [Label:] Mnemonic field OPTION : : ENDOP 11.1.2 Mask option definition quasi-directives The quasi-directives that can be used in the mask option definition block are listed in Table 10-1. The mask option definition can only be specified as follows. Be sure to specify the following quasi-directives. Example Symbol field Mnemonic field OPTION NOUSECAP ENDOP ; Capacitor for oscillation ; not incorporated Operand field Comment field Operand field Comment field [; Comment]
Table 11-1. Mask Option Definition Directives
Name Mask Option Definition Quasi-Directive PRO File Address Value CAP NOUSECAP (Capacitor for oscillation not incorporated) 2043H Data Value 00
60
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
12.WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY) (PD6P8)
The program memory of the PD6P8 is a one-time PROM of 2026 x 10 bits. To write or verify this one-time PROM, the pins shown in Table 5-1 are used. Note that no address input pin is used. Instead, the address is updated by using the clock input from the CLK pin. Table 12-1. Pins Used to Write/Verify Program Memory
Pin Name VPP VDD CLK MD0 to MD3 D0 to D7 XIN, XOUT Function Supplies voltage when writing/verifying program memory. Apply +10.5 V to this pin. Power supply. Supply +3 V to this pin when writing/verifying program memory. Inputs clock to update address when writing/verifying program memory. By inputting a pulse four times to the CLK pin, the address of the program memory is updated. Input to select the operation mode when writing/verifying program memory. Inputs/outputs 8-bit data when writing/verifying program memory. Clock necessary for writing program memory. Connect a 4 MHz ceramic resonator to this pin.
12.1 Operating Mode When Writing/Verifying Program Memory
The PD6P8 is set in the program memory write/verify mode when +10.5 V is applied to the VPP pin after the
PD6P8 has been in the reset status (VDD = 3 V, VPP = 0 V) for a specific time. In this mode, the operating modes
shown in Table 5-2 can be set by setting the MD0 through MD3 pins. Connect all the pins other than those shown in Table 5-1 to GND via pull-down resistors. Table 12-2. Setting Operating Mode
Setting of Operating Mode VPP +10.5 V VDD +3 V MD0 H L L H MD1 L H L x MD2 H H H H MD3 L H H H Clear program memory address to 0 Write mode Verify mode Program inhibit mode Operating Mode
x: don't care (L or H)
Data Sheet U17848EJ3V0DS
61
PD6P8, 6P8A, 6P8B
12.2 Program Memory Writing Procedure
The program memory is written at high speed by the following procedure. (1) (2) (3) (4) (5) (6) (7) (8) (9) Pull down the pins not used to GND via a resistor. Keep the CLK pin low. Supply 3 V to the VDD pin. Keep the VPP pin low. Supply 3 V to the VPP pin after waiting for 10 s. Wait for 2 ms until oscillation of the ceramic resonator connected across the XIN and XOUT pins stabilizes. Set the program memory address 0 clear mode by using the mode setting pins. Supply 10.5 V to VPP. Set the program inhibit mode. Input a pulse to the CLK pin four times. Write data to the program memory in the 100 s write mode. Set the program inhibit mode. steps (8) through (10). (11) Additional writing of (number of times of writing in (8) through (10): X) x 100 s. (12) Set the program inhibit mode. (13) Input a pulse to the CLK pin four times to update the program memory address (+1). (14) Repeat steps (8) through (13) up to the last address. (15) Set the 0 clear mode of the program memory address. (16) Change the voltages on the VPP pin to 3 V. (17) Turn off the power. The following figure illustrates steps (2) through (13) above.
Oscillation stabilization wait time
(10) Set the verify mode. If the data have been written to the program memory, proceed to (11). If not, repeat
Repeated X time Write Verify Additional write Address increment
Reset
VPP VPP VDD GND VDD VDD GND CLK
D0 to D7
Hi-Z
Data input
Hi-Z
Data output
Hi-Z
Data input
Hi-Z
MD0
MD1
MD2
MD3
62
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
12.3 Program Memory Reading Procedure
(1) (2) (3) (4) (5) (6) (7) (8) (9) Pull down the pins not used to GND via a resistor. Keep the CLK pin low. Supply 3 V to the VDD pin. Keep the VPP pin low. Supply 3 V to the VPP pin after waiting for 10 s. Wait for 2 ms until oscillation of the ceramic resonator connected across the XIN and XOUT pins stabilizes. Set the program memory address 0 clear mode by using the mode setting pins. Supply 10.5 V to VPP. Set the program inhibit mode. Input a pulse to the CLK pin four times. Set the verify mode. Data of each address is output sequentially each time the clock pulse is input to the CLK pin four times. Set the program inhibit mode. (10) Set the program memory address 0 clear mode. (11) Change the voltage on the VPP pin to 3 V. (12) Turn off the power. The following figure illustrates steps (2) through (10) above.
Reset VPP VPP VDD GND
Oscillation stabilization wait time
VDD
VDD GND CLK
D0 to D7
Hi-Z
Data output
Data output
Hi-Z
MD0
MD1
"L"
MD2
MD3
Data Sheet U17848EJ3V0DS
63
PD6P8, 6P8A, 6P8B
13.WRITING AND VERIFICATION OF ONE-TIME PROM (PROGRAM MEMORY) (PD6P8A, 6P8B)
The program memory built into the PD6P8A and 6P8B is a one-time PROM of 2026 x 10 bits. Writing or verification of this one-time PROM is performed using the pins listed in Table 13-1, and a 5-bit instruction and 5-bit data via serial communication. The assembler output has an 8-bit configuration, so mask the higher three bits and program the lower five bits. Table 13-1. Pins Used During Program Memory Writing/Verification
Pin No. 2 3 4 6 Symbol SO SCLK SI VDD Function Serial data output during program memory verification Clock input during program memory writing or verification Serial data input during program memory writing Power supply Supply +3 V to this pin during program memory writing or verification. 7 8 9 10 XOUT XIN GND VPP Clock required during program memory writing or verification. Connect a 4 MHz ceramic resonator to these pins. GND Voltage application pin during program memory writing or verification. Apply +10.5 V to this pin. Input - - - I/O Output Input Input -
13.1 Initialization
When a high voltage (10.5 V) is supplied to VPP, the programming mode is set after about 1 ms. In the programming mode, pins not used for programming are pulled down internally, so leave them open. S1/LED is set to output mode (H) when 3 V is supplied to VDD and VPP. When a high voltage (10.5 V) is supplied to VPP, the input mode is set after about 1 ms. Serial communication is performed in 5-bit units, starting from the MSB.
64
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
Perform initialization according to the following procedure. (1) (2) (3) (4) (5) (6) (7) Supply 3 V to the VDD pin. Set the VPP pin to low level. Supply 3 V (same potential as VDD) to the VPP pin after waiting for 10 s. Wait for 2 ms until oscillation stabilizes. Supply 10.5 V to the VPP pin. Wait for 1 ms until oscillation stabilizes. Transmit the PCRESET instruction from the programmer. Transmit the SSVERIFY instruction from the programmer for silicon signature verification.
1 VPP (10.5 V) VPP VDD GND
2
3
4
5
6
7
10 s VDD VDD GND
13.2 Serial Communication Format
Instruction Data
All instructions consist of a 5-bit instruction and 5-bit data. The data from the programmer is latched at the rising edge of SCLK. The PD6P8A and 6P8B output data is output at the falling edge of SCLK. Instruction format
4 MD4 3 MD3 2 MD2 1 MD1 0 MD0 Function Clearing the program memory address to 0 Verify mode Write mode Incrementing of the program memory address Silicon signature verify mode Program inhibit mode
MD4 to MD0 05 0C 0E 11 08 01
Instruction Reset Verify Program Increment Signature verify Inhibit
Data Sheet U17848EJ3V0DS
65
PD6P8, 6P8A, 6P8B
13.3 Writing of Program Memory
Program command
Program data
VPP
SCLK SI
CI4 CI3 CI2 CI1 CI0 0 1 1 1 0 CI4 CI3 CI2 CI1 CI0
SO
13.4 Reading of Program Memory
Verify command
Read data
VPP
SCLK SI
CI4 CI3 CI2 CI1 CI0 0 1 1 0 0 DO4 DO3 DO2 DO1 DO1
SO
66
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
14. ELECTRICAL SPECIFICATIONS (PD6P8)
Absolute Maximum Ratings (TA = +25C)
Parameter Power supply voltage Symbol VDD VPP Input voltage Output voltage Output current, high VI VO IOHNote REM Peak value rms LED Peak value rms Per KI/O0-KI/O7 pin Peak value rms Total for LED and KI/O0-KI/O7 pins Output current, low IOLNote REM Peak value rms Peak value rms LED Peak value rms Operating ambient temperature Storage temperature TA Tstg KI/O0-KI/O7, KI0-KI3, S0, S1, S2 Conditions Rating -0.3 to +5.0 -0.3 to +11.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -30 -20 -7.5 -5 -13.5 -9 -18 -12 7.5 5 7.5 5 -40 to +85 -65 to +150 Unit V V V V mA mA mA mA mA mA mA mA mA mA mA mA C C
Note Calculate the rms with: [rms] = [Peak value] x Duty. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Power Supply Voltage Range (TA = -40 to +85C)
Parameter Power supply voltage Symbol VDD Conditions fX = 3.5 to 4.5 MHz MIN. 1.9 TYP. 3.0 MAX. 3.6 Unit V
Data Sheet U17848EJ3V0DS
67
PD6P8, 6P8A, 6P8B
DC Characteristics (TA = -40 to +85C, VDD = 1.9 to 3.6 V)
Item Input voltage, high Symbol VIH1 VIH2 Input voltage, low VIL1 VIL2 Input leakage current, high ILIH1 ILIH2 Input leakage current, low ILIL1 ILIL2 ILIL3 Output voltage, high Output voltage, low VOH1 VOL1 VOL2 Output current, high IOH1 IOH2 Output current, low IOL1 KI/O0-KI/O7 KI0-KI3, S0, S1, S2 KI/O0-KI/O7 KI0-KI3, S0, S1, S2 KI0-KI3 VI = VDD, pull-down resistor not incorporated S0, S1, S2 VI = VDD, pull-down resistor not incorporated KI0-KI3 VI = 0 V Conditions MIN. 0.7VDD 0.65VDD 0 0 TYP. MAX. VDD VDD 0.3VDD 0.15VDD 3 3 -3 -3 -3 0.8VDD 0.3 0.4 -5 -2.5 30 100 75 130 1.2 1.8 Operation mode HALT mode STOP mode fX = 4.0 MHz, VDD = 3 V 10% fX = 4.0 MHz, VDD = 3 V 10% VDD = 3 V 10% VDD = 3 V 10%, TA = 25C 1.1 1.0 2.2 2.2 -9 -5 70 220 150 250 300 500 3.6 1.9 2.2 2.0 9.5 3.5 Unit V V V V
A A A A A
V V V mA mA
KI/O0-KI/O7 VI = 0 V S0, S1, S2 VI = 0 V REM, LED, KI/O0-KI/O7 IOH = -0.3 mA REM, LED KI/O0-KI/O7 REM KI/O0-KI/O7 KI/O0-KI/O7 IOL = 0.3 mA IOL = 15 A VDD = 3.0 V, VOH = 1.0 V VDD = 3.0 V, VOH = 2.2 V VDD = 3.0 V, VOL = 0.4 V VDD = 3.0 V, VOL = 2.2 V
A A
k k V V mA mA
On-chip pull-down resistor
R1 R2
KI0-KI3, S0, S1, S2 KI/O0-KI/O7 In STOP mode
Data retention power supply voltage RAM retention detection voltage Supply current
VDDOR VID IDD1 IDD2 IDD3
A A
68
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
AC Characteristics (TA = -40 to +85C, VDD = 1.9 to 3.6 V)
Parameter Instruction execution time KI0-KI3, S0, S1 high-level width Symbol tCY tH When releasing standby mode In HALT mode In STOP mode RESET low-level width tRSL Conditions MIN. 14 10 10 Note 10 TYP. 16 MAX. 18.5 Unit
s s s s s
Note 10 + 284/fX + oscillation growth time Remark tCY = 64/fX (fX: System clock oscillation frequency) POC Circuit (TA = -40 to +85C)
Parameter POC detection voltageNote Symbol VPOC Conditions MIN. TYP. 1.8 MAX. 1.9 Unit V
Note Refers to the voltage with which the POC circuit releases an internal reset. If VPOC < VDD, the internal reset is released. From the time of VPOC VDD until the internal reset takes effect, lag of up to 1 ms occurs. When the period of VPOC VDD lasts less than 1 ms, the internal reset may not take effect. System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.9 to 3.6 V)
Parameter Oscillation frequency (ceramic resonator) Symbol fX Conditions MIN. 3.5 TYP. 4.0 MAX. 4.5 Unit MHz
External circuit example
XIN
XOUT
C1
C2
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U17848EJ3V0DS
69
PD6P8, 6P8A, 6P8B
RECOMMENDED OSCILLATOR CONSTANT
Ceramic Resonator (TA = -40 to +85C)
Manufacturer Part Number Frequency Recommended Constant (pF) (MHz) Murata Mfg. Co., Ltd. CSTCC3M50G56-R0 CSTLS3M50G56-B0 CSTCC3M64G56-R0 CSTLS3M64G56-B0 CSTCR4M00G55-R0 CSTLS4M00G56-B0 CSTCR4M19G55-R0 CSTLS4M19G56-B0 CSTCR4M50G55-R0 CSTLS4M50G56-B0 4.50 4.19 4.00 3.64 3.50 C1 C2 1.9 Oscillation Voltage Range (VDD) MIN. 3.6 MAX. - Remark
Unnecessary (on-chip C type)
External circuit example
XIN
XOUT
C1
C2
Caution These oscillator constants are reference values based on evaluation by the manufacturer of the resonator under a specific environment. If optimization of the oscillator characteristics is required for the actual application, apply to the resonator manufacturer for evaluation on the mounting circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristics; the oscillator must be used within the ratings of the DC and AC characteristics specified under the internal operation conditions. Remark The incorporation of the oscillation capacitor by a mask option is under evaluation.
70
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
PROM Programming Mode DC programming characteristics (TA = 25C, VDD = 3.0 0.3 V, VPP = 10.5 0.3 V)
Parameter Input voltage, high Symbol VIH1 VIH2 Input voltage, low VIL1 VIL2 Input leakage current Output voltage, high Output voltage, low VDD supply current VPP supply current ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Conditions Other than CLK CLK Other than CLK CLK VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD - 1.0 0.4 30 30 MIN. 0.7VDD VDD - 0.5 0 0 TYP. MAX. VDD VDD 0.3VDD 0.4 10 Unit V V V V
A
V V mA mA
Cautions 1. Keep VPP to within +11.0 V including overshoot. 2. Apply VDD before VPP and turns it off after VPP.
Data Sheet U17848EJ3V0DS
71
PD6P8, 6P8A, 6P8B
AC programming characteristics (TA = 25C, VDD = 3.0 0.3 V, VPP = 10.5 0.3 V)
Parameter Address setup timeNote 1 (to MD0) MD1 setup time (to MD0) Data setup time (to MD0) Address hold timeNote 1 (from MD0) Symbol tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tMOS tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR to data output tOAD tHAD tM3HR tDFR tRES tWAIT
When program memory is read When program memory is read When program memory is read When program memory is read When program memory is read
Conditions
MIN. 2 2 2 2 2 0 2 2 0.095 0.095 2
TYP.
MAX.
Unit
s s s s s
4
Data hold time (from MD0) Delay time from MD0 to data output float VPP setup time (to MD3) VDD setup time (to MD3) Initial program pulse width Additional program pulse width MD0 setup time (to MD1) Delay time from MD0 to data output MD1 hold time (from MD0) MD1 recovery time (to MD0) Program counter reset time CLK input high-/low-level width CLK input frequency Initial mode set time MD3 setup time (to MD1) MD3 hold time (from MD1) MD3 setup time (to MD0) Delay time from addressNote 1 Hold time from addressNote 1 to data output MD3 hold time (from MD0) Delay time from MD3 to data output float Reset setup time Oscillation stabilization wait timeNote 2
s s s
0.1
0.105 2.1
ms ms
s
4
MD0 = MD1 = VIL tM1H+tM1R 50 s 2 2 10 0.125
s s s s s
4.19 2 2 2 2 4 0 2 4 10 2 4
MHz
s s s s s s s s s
ms
Notes 1. The internal address signal is incremented at the falling edge of the third clock of CLK. 2. Connect a 4 MHz ceramic resonator between the XIN and XOUT pins.
72
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
Program Memory Write Timing
tWAIT VPP VDD GND VDD GND CLK Hi-Z tI MD0 tPW MD1 tPCR MD2 tM3S MD3 tM3H tM1S tM1H tM1R tMOS tOPW tXL
Data input
tRES
tVPS
VPP
VDD
tXH
tXH
D0 to D7
Hi-Z tDH
Data output
Hi-Z
tXL
Data input
Hi-Z tAS
Data input
Hi-Z
tDS tAS
tDV
tDF
tDS
tDH tAH
Program Memory Read Timing
tWAIT tRES tVPS VPP VPP VDD GND VDD GND CLK tXL D0-D7 tI MD0 tXL Hi-Z tDV tDV tM3HR tDFR
Data output
VDD
tXH
tXH
tDAD tHAD
Data output
Hi-Z
MD1 tPCR MD2 tM3SR MD3
"L"
Data Sheet U17848EJ3V0DS
73
PD6P8, 6P8A, 6P8B
15. ELECTRICAL SPECIFICATIONS (PD6P8A)
Absolute Maximum Ratings (TA = +25C)
Parameter Power supply voltage Symbol VDD VPP Input voltage Output voltage Output current, high VI VO IOHNote REM Peak value rms LED Peak value rms Per KI/O0-KI/O7 pin Peak value rms Total for LED and KI/O0-KI/O7 pins Output current, low IOLNote REM Peak value rms Peak value rms LED Peak value rms Operating ambient temperature Storage temperature TA Tstg KI/O0-KI/O7, KI0-KI3, S0, S1, S2 Conditions Rating -0.3 to +5.0 -0.3 to +11.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -30 -20 -7.5 -5 -13.5 -9 -18 -12 7.5 5 7.5 5 -40 to +85 -65 to +150 Unit V V V V mA mA mA mA mA mA mA mA mA mA mA mA C C
Note Calculate the rms with: [rms] = [Peak value] x Duty. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Power Supply Voltage Range (TA = -40 to +85C)
Parameter Power supply voltage Symbol VDD Conditions fX = 3.5 to 4.5 MHz MIN. 1.9 TYP. 3.0 MAX. 3.6 Unit V
74
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
DC Characteristics (TA = -40 to +85C, VDD = 1.9 to 3.6 V)
Item Input voltage, high Symbol VIH1 VIH2 Input voltage, low VIL1 VIL2 Input leakage current, high ILIH1 ILIH2 Input leakage current, low ILIL1 ILIL2 ILIL3 Output voltage, high Output voltage, low VOH1 VOL1 VOL2 Output current, high IOH1 IOH2 Output current, low IOL1 KI/O0-KI/O7 KI0-KI3, S0, S1, S2 KI/O0-KI/O7 KI0-KI3, S0, S1, S2 KI0-KI3 VI = VDD, pull-down resistor not incorporated S0, S1, S2 VI = VDD, pull-down resistor not incorporated KI0-KI3 VI = 0 V Conditions MIN. 0.7VDD 0.65VDD 0 0 TYP. MAX. VDD VDD 0.3VDD 0.15VDD 3 3 -3 -3 -3 0.8VDD 0.3 0.4 -5 -2.5 30 100 75 130 1.2 1.6 Operation mode HALT mode STOP mode fX = 4.0 MHz, VDD = 3 V 10% fX = 4.0 MHz, VDD = 3 V 10% VDD = 3 V 10% VDD = 3 V 10%, TA = 25C 0.7 0.65 2.2 2.2 -9 -5 70 220 150 250 300 500 3.6 1.7 1.4 1.3 9.5 3.5 Unit V V V V
A A A A A
V V V mA mA
KI/O0-KI/O7 VI = 0 V S0, S1, S2 VI = 0 V REM, LED, KI/O0-KI/O7 IOH = -0.3 mA REM, LED KI/O0-KI/O7 REM KI/O0-KI/O7 KI/O0-KI/O7 IOL = 0.3 mA IOL = 15 A VDD = 3.0 V, VOH = 1.0 V VDD = 3.0 V, VOH = 2.2 V VDD = 3.0 V, VOL = 0.4 V VDD = 3.0 V, VOL = 2.2 V
A A
k k V V mA mA
On-chip pull-down resistor
R1 R2
KI0-KI3, S0, S1, S2 KI/O0-KI/O7 In STOP mode
Data retention power supply voltage RAM retention detection voltage
VDDOR VID IDD1 IDD2 IDD3

Supply current
A A
Data Sheet U17848EJ3V0DS
75
PD6P8, 6P8A, 6P8B
AC Characteristics (TA = -40 to +85C, VDD = 1.9 to 3.6 V)
Parameter Instruction execution time KI0-KI3, S0, S1 high-level width Symbol tCY tH When releasing standby mode In HALT mode In STOP mode RESET low-level width tRSL Conditions MIN. 14 10 10 Note 10 TYP. 16 MAX. 18.5 Unit
s s s s s

Note 10 + 1024/fX + oscillation growth time Remark tCY = 64/fX (fX: System clock oscillation frequency) POC Circuit (TA = -40 to +85C)
Parameter POC detection voltageNote Symbol VPOC Conditions MIN. TYP. 1.8 MAX. 1.9 Unit V
Note Refers to the voltage with which the POC circuit releases an internal reset. If VPOC < VDD, the internal reset is released. From the time of VPOC VDD until the internal reset takes effect, lag of up to 1 ms occurs. When the period of VPOC VDD lasts less than 1 ms, the internal reset may not take effect. System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.9 to 3.6 V)
Parameter Oscillation frequency (ceramic resonator) Symbol fX Conditions MIN. 3.5 TYP. 4.0 MAX. 4.5 Unit MHz
External circuit example
XIN
XOUT
C1
C2
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
76
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
PROM Programming Mode DC programming characteristics (TA = 25C, VDD = 3.0 0.3 V, VPP = 10.5 0.3 V)
Parameter Input voltage, high Symbol VIH1 VIH2 Input voltage, low VIL1 VIL2 Input leakage current Output voltage, high Output voltage, low VDD supply current VPP supply current ILI VOH VOL IDD IPP Conditions Other than SCLK SCLK Other than SCLK SCLK VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD - 1.0 0.4 2 0.3 MIN. 0.7VDD VDD - 0.5 0 0 TYP. MAX. VDD VDD 0.3VDD 0.4 10 Unit V V V V
A
V V mA mA
Cautions 1. Keep VPP to within +11.0 V including overshoot. 2. Apply VDD before VPP and turns it off after VPP. AC programming characteristics (TA = 25C, VDD = 3.0 0.3 V, VPP = 10.5 0.3 V)
Parameter Reset setup time Oscillation stabilization wait time1 Oscillation stabilization wait time2 SCLK cycle time VPP setup time (to Program command) Program command Data input wait time Program data Command input wait time VPP setup time (to Verify command) Verify command Data output wait time Verify data Command input wait time VPP setup time (to Reset, Increase, Inhibit command) Reset, Increase, Inhibit command Data (NULL) input wait time Reset, Increase, Inhibit command Command input wait time tOT 0.25 tOI 0.25 Symbol tRES tWAIT1 tWAIT2 tKCY tWA tWI tWR tRA tRI tRE tOA 1.8 0.25 90 1.8 5 0.25 1.8 Conditions MIN. 10 2 1 1 TYP. MAX. Unit
s
ms ms MHz ms
s s
ms
s s
ms
s s
Data Sheet U17848EJ3V0DS
77
PD6P8, 6P8A, 6P8B
Program Memory Access Timing
tRES VPP VPP VDD GND VDD GND SCLK
tWAIT1
tWA, tRA, tWAIT2 tOA
tKCY
tWI, tRI, tOI
tWR, tRE, tOT
SI
CI4 CI3 CI2 CI1 CI0
CI4 CI3 CI2 CI1 CI0
SO
DO4 DO3 DO2 DO1 DO0
78
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
16. ELECTRICAL SPECIFICATIONS (PD6P8B) (TARGET)
Absolute Maximum Ratings (TA = +25C)
Parameter Power supply voltage Symbol VDD VPP Input voltage Output voltage Output current, high VI VO IOHNote REM Peak value rms LED Peak value rms Per KI/O0-KI/O7 pin Peak value rms Total for LED and KI/O0-KI/O7 pins Output current, low IOLNote REM Peak value rms Peak value rms LED Peak value rms Operating ambient temperature Storage temperature TA Tstg KI/O0-KI/O7, KI0-KI3, S0, S1, S2 Conditions Rating -0.3 to +5.0 -0.3 to +11.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -30 -20 -7.5 -5 -13.5 -9 -18 -12 7.5 5 7.5 5 -40 to +85 -65 to +150 Unit V V V V mA mA mA mA mA mA mA mA mA mA mA mA C C
Note Calculate the rms with: [rms] = [Peak value] x Duty. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Power Supply Voltage Range (TA = -40 to +85C)
Parameter Power supply voltage Symbol VDD Conditions fX = 3.5 to 4.5 MHz MIN. 1.9 TYP. 3.0 MAX. 3.6 Unit V
Data Sheet U17848EJ3V0DS
79
PD6P8, 6P8A, 6P8B
DC Characteristics (TA = -40 to +85C, VDD = 1.9 to 3.6 V)
Item Input voltage, high Symbol VIH1 VIH2 Input voltage, low VIL1 VIL2 Input leakage current, high ILIH1 ILIH2 Input leakage current, low ILIL1 ILIL2 ILIL3 Output voltage, high Output voltage, low VOH1 VOL1 VOL2 Output current, high IOH1 IOH2 Output current, low IOL1 KI/O0-KI/O7 KI0-KI3, S0, S1, S2 KI/O0-KI/O7 KI0-KI3, S0, S1, S2 KI0-KI3 VI = VDD, pull-down resistor not incorporated S0, S1, S2 VI = VDD, pull-down resistor not incorporated KI0-KI3 VI = 0 V Conditions MIN. 0.7VDD 0.65VDD 0 0 TYP. MAX. VDD VDD 0.3VDD 0.15VDD 3 3 -3 -3 -3 0.8VDD 0.3 0.4 -5 -2.5 30 100 75 130 1.2 1.6 Operation mode HALT mode STOP mode fX = 4.0 MHz, VDD = 3 V 10% fX = 4.0 MHz, VDD = 3 V 10% VDD = 3 V 10% VDD = 3 V 10%, TA = 25C 0.7 0.65 2.2 2.2 -9 -5 70 220 150 250 300 500 3.6 1.7 1.4 1.3 9.5 3.5 Unit V V V V
A A A A A
V V V mA mA
KI/O0-KI/O7 VI = 0 V S0, S1, S2 VI = 0 V REM, LED, KI/O0-KI/O7 IOH = -0.3 mA REM, LED KI/O0-KI/O7 REM KI/O0-KI/O7 KI/O0-KI/O7 IOL = 0.3 mA IOL = 15 A VDD = 3.0 V, VOH = 1.0 V VDD = 3.0 V, VOH = 2.2 V VDD = 3.0 V, VOL = 0.4 V VDD = 3.0 V, VOL = 2.2 V
A A
k k V V mA mA
On-chip pull-down resistor
R1 R2
KI0-KI3, S0, S1, S2 KI/O0-KI/O7 In STOP mode
Data retention power supply voltage RAM retention detection voltage Supply current
VDDOR VID IDD1 IDD2 IDD3
A A
80
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
AC Characteristics (TA = -40 to +85C, VDD = 1.9 to 3.6 V)
Parameter Instruction execution time KI0-KI3, S0, S1 high-level width Symbol tCY tH When releasing standby mode In HALT mode In STOP mode RESET low-level width tRSL Conditions MIN. 14 10 10 Note 10 TYP. 16 MAX. 18.5 Unit
s s s s s

Note 10 + 1024/fX + oscillation growth time Remark tCY = 64/fX (fX: System clock oscillation frequency) POC Circuit (TA = -40 to +85C)
Parameter POC detection voltageNote Symbol VPOC Conditions MIN. TYP. 1.8 MAX. 1.9 Unit V
Note Refers to the voltage with which the POC circuit releases an internal reset. If VPOC < VDD, the internal reset is released. From the time of VPOC VDD until the internal reset takes effect, lag of up to 1 ms occurs. When the period of VPOC VDD lasts less than 1 ms, the internal reset may not take effect. Internal Oscillator Characteristics (TA = -10 to +70C, VDD = 2.0 to 3.6 V)
Parameter Oscillation frequency Symbol fX Conditions MIN. 3.92 TYP. 4.0 MAX. 4.08 Unit MHz
Data Sheet U17848EJ3V0DS
81
PD6P8, 6P8A, 6P8B
PROM Programming Mode DC programming characteristics (TA = 25C, VDD = 3.0 0.3 V, VPP = 10.5 0.3 V)
Parameter Input voltage, high Symbol VIH1 VIH2 Input voltage, low VIL1 VIL2 Input leakage current Output voltage, high Output voltage, low VDD supply current VPP supply current ILI VOH VOL IDD IPP Conditions Other than SCLK SCLK Other than SCLK SCLK VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD - 1.0 0.4 2 0.3 MIN. 0.7VDD VDD - 0.5 0 0 TYP. MAX. VDD VDD 0.3VDD 0.4 10 Unit V V V V
A
V V mA mA
Cautions 1. Keep VPP to within +11.0 V including overshoot. 2. Apply VDD before VPP and turns it off after VPP. AC programming characteristics (TA = 25C, VDD = 3.0 0.3 V, VPP = 10.5 0.3 V)
Parameter Reset setup time Oscillation stabilization wait time1 Oscillation stabilization wait time2 SCLK cycle time VPP setup time (to Program command) Program command Data input wait time Program data Command input wait time VPP setup time (to Verify command) Verify command Data output wait time Verify data Command input wait time VPP setup time (to Reset, Increase, Inhibit command) Reset, Increase, Inhibit command Data (NULL) input wait time Reset, Increase, Inhibit command Command input wait time tOT 0.25 tOI 0.25 Symbol tRES tWAIT1 tWAIT2 tKCY tWA tWI tWR tRA tRI tRE tOA 1.8 0.25 90 1.8 5 0.25 1.8 Conditions MIN. 10 2 1 1 TYP. MAX. Unit
s
ms ms MHz ms
s s
ms
s s
ms
s s
82
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
Program Memory Access Timing
tRES VPP VPP VDD GND VDD GND SCLK
tWAIT1
tWA, tRA, tWAIT2 tOA
tKCY
tWI, tRI, tOI
tWR, tRE, tOT
SI
CI4 CI3 CI2 CI1 CI0
CI4 CI3 CI2 CI1 CI0
SO
DO4 DO3 DO2 DO1 DO0
Data Sheet U17848EJ3V0DS
83
PD6P8, 6P8A, 6P8B
17. CHARACTERISTIC CURVES (REFERENCE VALUES) (PD6P8)
IDD vs. VDD (fx = 4 MHz) (TA = 25C) 1 0.9
Power supply current IDD [mA] Low-level output current IOL [mA]
IOL vs. VOL (REM, LED) (TA = 25C, VDD = 3.0 V) 25
0.8 0.7 0.6 0.5 0.4 HALT mode 0.3 0.2 0.1 0 1.5 2 2.5 3 3.6 4 Operation mode
20
15
10
5
0
1
2
3
Power supply voltage VDD [V]
Low-level output voltage VOL [V]
- 20
High-level output current IOH [mA]
IOH vs. VOH (REM, LED, KI/O) (TA = 25C, VDD = 3.0 V) 500 450
Low-level output current IOL [ A]
IOL vs. VOL (KI/O) (TA = 25C, VDD = 3.0 V)
- 18 - 16 - 14 - 12 - 10 -8 -6 -4 -2 0 VDD VDD - 1 VDD - 2 VDD - 3
400 350 300 250 200 150 100 50 0 1 2 Low-level output voltage VOL [V] 3
High-level output voltage VOH [V]
84
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
18. APPLICATION CIRCUIT EXAMPLE Example of Application to System * Remote-control transmitter (48 keys accommodated, mode selection switch accommodated)
KI/O6 KI/O7 S0 + S1/LED REM VDD XOUT XIN GND S2 Mode select switch
Note
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0 Key matrix 8 x 6 = 48 keys
Note S2: Set to STOP mode release disabled
Data Sheet U17848EJ3V0DS
85
PD6P8, 6P8A, 6P8B
* Remote-control transmitter (56 keys accommodated)
KI/O6 KI/O7 S0 + S1/LED REM VDD XOUT XIN GND S2Note
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0 Key matrix 8 x 7 = 56 keys
Note S2: Set to STOP mode release enabled
86
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
* Remote-control transmitter (56 keys accommodated, mode selection switch accommodated) Data can be read from the KI/O0 to KI/O7 pins by connecting a pull-up resistor of approx. 50 k and a switch to these pins (which then become high level when the switch is on and low level when off). Set the KI/O0 to KI/O7 pins to input mode at this time. Reading data from these pins enables multiple output data to be obtained for the same key input. A pull-up resistor can be connected to any of pins KI/O0 to KI/O7 (the figure below shows an example of when a pull-up resistor is connected to the KI/O5 pin).
VDD Mode selection switch
KI/O6 KI/O7 S0 + S1/LED REM VDD XOUT XIN GND S2Note
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0 Key matrix 8 x 7 = 56 keys
Note S2: Set to STOP mode release enabled
Data Sheet U17848EJ3V0DS
87
PD6P8, 6P8A, 6P8B
19. PACKAGE DRAWING
20-PIN PLASTIC SSOP (7.62 mm (300))
20 11
detail of lead end F G T
P E 1 A H I S 10
L U
J
N C D
NOTE
S K
M
M
B
(UNIT:mm) ITEM A B C D E F G H I J K L M N P T U MILLIMETERS 6.650.15 0.475 MAX. 0.65 (T.P.) 0.24 +0.08 -0.07 0.10.05 1.30.1 1.2 8.10.2 6.10.2 1.00.2 0.170.03 0.5 0.13 0.10 3 +5 -3 0.25 0.60.15 S20MC-65-5A4-2
Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
88
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
20. RECOMMENDED SOLDERING CONDITIONS
The PD6P8, 6P8A, and 6P8B must be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 20-1. Surface Mounting Soldering Conditions
PD6P8MC-5A4-A, 6P8AMC-5A4-A, 6P8BMC-5A4-A: 20-pin plastic SSOP (7.62 mm (300))
Recommended Condition Symbol IR60-207-3
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Count: Three times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 2 to 72 hours) For details, contact an NEC Electronics sales representative. Pin temperature: 350C max., Time: 3 seconds max. (per pin row)
Wave soldering Partial heating
- -
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remark Products that have the part numbers suffixed by "-A" are lead-free products.
Data Sheet U17848EJ3V0DS
89
PD6P8, 6P8A, 6P8B
APPENDIX A. DEVELOPMENT TOOLS
A PROM programmer, program adapter, and an emulator are provided for the PD6P8, 6P8A, 6P8B. Hardware * PROM programmer (AF-9708Note, AF-9709BNote) These PROM programmers support the PD6P8, 6P8A, 6P8B. By connecting a program adapter to this PROM programmer, the PD6P8, 6P8A, 6P8B can be programmed. Note These are products of Flash Support Group, Inc. For details, consult Flash Support Group, Inc. (TEL: +81-53-428-8380). * Program adapter (1) TEF340-6P8Note This is used to program the PD6P8 in combination with the AF-9708 or AF-9709B. (2) TEF340-6P8ANote This is used to program the PD6P8A, 6P8B in combination with the AF-9708 or AF-9709B. Note These are products of Flash Support Group, Inc. For details, consult Flash Support Group, Inc. (TEL: +81-53-428-8380). * Emulator (EB-69Note, EB-69ANote) This is used to emulate the PD6P8, 6P8A, 6P8B. Note These are products of Naito Densei Machida Mfg. Co., Ltd. For details, contact Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191). Software * Assembler (AS6133 Ver. 2.22 or later) This is a development tool for remote control transmitter software. Part Number List of AS6133
Host Machine PC-9800 series (CPU: 80386 or later) IBM PC/ATTM compatible OS MS-DOSTM (Ver. 5.0 to Ver. 6.2) MS-DOS (Ver. 6.0 to Ver. 6.22) PC DOSTM (Ver. 6.1 to Ver. 6.3) Supply Medium 3.5-inch 2HD 3.5-inch 2HC Part Number
S5A13AS6133 S7B13AS6133
Caution Although Ver.5.0 or later has a task swap function, this function cannot be used with this software.
90
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
APPENDIX B. EXAMPLE OF REMOTE CONTROL TRANSMISSION FORMAT (In the case of NEC transmission format in command one-shot transmission mode)
Caution When using the NEC transmission format, please apply for a custom code at NEC Electronics. (1) REM output waveform (from <2> on, the output is made only when the key is kept pressed)
REM output 58.5 to 76.5 ms <1> 108 ms
<2> 108 ms
Remark If the key is repeatedly pressed, the power consumption of the infrared light-emitting diode (LED) can be reduced by sending the reader code and the stop bit from the second time. (2) Enlarged waveform of <1>
<3> REM output 9 ms 4.5 ms Custom code 8 bits Custom code' 8 bits Data code 8 bits 27 ms Data code 8 bits Stop Bit 1 bit
13.5 ms Leader code
18 to 36 ms 58.5 to 76.5 ms
(3) Enlarged waveform of <3>
REM output 9 ms 13.5 ms 4.5 ms 0.56 ms 1.125 ms 2.25 ms 1 0
1
0
0
(4) Enlarged waveform of <2>
REM output 9 ms 11.25 ms Leader code 2.25 ms 0.56 ms Stop Bit
Data Sheet U17848EJ3V0DS
91
PD6P8, 6P8A, 6P8B
(5) Carrier waveform (enlarged waveform of each code's high period)
REM output 8.77 s 26.3 s 9 ms or 0.56 ms Carrier frequency: 38 kHz
(6) Bit array of each code
C0 C1 C2 C3 C4 C5 C6 C7 C0' C1' C2' C3' C4' C5' C6' C7' D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
= = = = = = = =
C0 C1 C2 C3 C4 C5 C6 C7 or or or or or or or or C8 C9 C10 C11 C12 C13 C14 C15
Leader code
Custom code
Custom code'
Data code
Data code
Caution To prevent malfunction with other systems when receiving data in the NEC transmission format, not only fully decode (make sure to check Data Code as well) the total 32 bits of the 16-bit custom codes (Custom Code, Custom Code') and the 16-bit data codes (Data Code, Data Code) but also check to make sure that no signals are present.
92
Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
NOTES FOR CMOS DEVICES
1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.
Data Sheet U17848EJ3V0DS
93
PD6P8, 6P8A, 6P8B
MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT and PC DOS are trademarks of International Business Machines Corporation.
Caution: This product uses SuperFlash technology licensed from Silicon Storage Technology, Inc.
* The information in this document is current as of December, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1
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Data Sheet U17848EJ3V0DS
PD6P8, 6P8A, 6P8B
For further information, please contact:
NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [America] NEC Electronics America, Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554, U.S.A. Tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ [Europe] NEC Electronics (Europe) GmbH Arcadiastrasse 10 40472 Dusseldorf, Germany Tel: 0211-65030 http://www.eu.necel.com/ Hanover Office Podbielskistrasse 166 B 30177 Hannover Tel: 0 511 33 40 2-0 Munich Office Werner-Eckert-Strasse 9 81829 Munchen Tel: 0 89 92 10 03-0 Stuttgart Office Industriestrasse 3 70565 Stuttgart Tel: 0 711 99 01 0-0 United Kingdom Branch Cygnus House, Sunrise Parkway Linford Wood, Milton Keynes MK14 6NP, U.K. Tel: 01908-691-133 Succursale Francaise 9, rue Paul Dautier, B.P. 52 78142 Velizy-Villacoublay Cedex France Tel: 01-3067-5800 Sucursal en Espana Juan Esplandiu, 15 28007 Madrid, Spain Tel: 091-504-2787 Tyskland Filial Taby Centrum Entrance S (7th floor) 18322 Taby, Sweden Tel: 08 638 72 00 Filiale Italiana Via Fabio Filzi, 25/A 20124 Milano, Italy Tel: 02-667541 Branch The Netherlands Steijgerweg 6 5616 HS Eindhoven The Netherlands Tel: 040 265 40 10
G0706
[Asia & Oceania] NEC Electronics (China) Co., Ltd 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian District, Beijing 100083, P.R.China Tel: 010-8235-1155 http://www.cn.necel.com/ Shanghai Branch Room 2509-2510, Bank of China Tower, 200 Yincheng Road Central, Pudong New Area, Shanghai, P.R.China P.C:200120 Tel:021-5888-5400 http://www.cn.necel.com/ Shenzhen Branch Unit 01, 39/F, Excellence Times Square Building, No. 4068 Yi Tian Road, Futian District, Shenzhen, P.R.China P.C:518048 Tel:0755-8282-9800 http://www.cn.necel.com/ NEC Electronics Hong Kong Ltd. Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: 2886-9318 http://www.hk.necel.com/ NEC Electronics Taiwan Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan, R. O. C. Tel: 02-8175-9600 http://www.tw.necel.com/ NEC Electronics Singapore Pte. Ltd. 238A Thomson Road, #12-08 Novena Square, Singapore 307684 Tel: 6253-8311 http://www.sg.necel.com/ NEC Electronics Korea Ltd. 11F., Samik Lavied'or Bldg., 720-2, Yeoksam-Dong, Kangnam-Ku, Seoul, 135-080, Korea Tel: 02-558-3737 http://www.kr.necel.com/

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